Usage of DCACHE_InvalidateByRange() in SDRAM code

[Jeevan]

Hi team,

we are using a custom board with imxrt1176xxx and the same SDRAM (SDRAM-w9825g6kh) which is used on imxrt1170 eval board.

Hardware connection wise is everything same as the eval board.

when we are doing 32 bit write and read, data is not matching and when we do 16 bit, 8 bit write and read also some dataline in the SEMC is toggling the bit from 0 to 1.

What is the purpose of below functionality as its affecting the read cycle in our custom board?

And in some custom board we need to read first the SDRAM and then write and read the SDRAM to properly match the write and read data, that too making the above DCACHE function disabled.

[Sam_Gao]

Hi,

It seems there are some questions about SDRAM for the new custom board, I would like to give comments into seperate ones.

Questions1: Hardware connection wise is everything same as the eval board. 32 bit writting and reading failed, but seems work fine when doing 16 bit, 8 bit write and read.

- Would you please check hardware from timing frequency, especially for abnormal 32bits case? It should be checked whether the SDRAM timing parameters are configured correctly

Questions2: What is the purpose of 'DCACHE_CleanInvalidateByRange'?  why its affecting the read cycle in our custom board about question1?

- The function 'DCACHE_xxx' is for CACHE aligment, it is strange for that.

- Would you please check with following patch for this board? and please make sure if this issue can be 100% reproduced for all custom board.

1. Set this marco to 0

// #define CACHE_MAINTAIN 0x01U
 #define CACHE_MAINTAIN 0

2. source/semc_sdram.c, add " SCB_DisableDCache()" before reading or writing.

int main(void)
{
	/* Hardware initialize. */
	BOARD_ConfigMPU();
	BOARD_InitPins();
	BOARD_BootClockRUN();
	BOARD_InitDebugConsole();

	/* Config cacheable attribute for SDRAM memory */
	APP_ConfigMPU();

#if !(defined(CACHE_MAINTAIN) && CACHE_MAINTAIN)
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
	if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
	{
		SCB_DisableDCache();
	}
#endif
#endif

	PRINTF("\r\n SEMC SDRAM Example Start!\r\n");
	if (BOARD_InitSEMC() != kStatus_Success)
	{
		PRINTF("\r\n SEMC SDRAM Init Failed\r\n");
	}

+       SCB_DisableDCache();
	/* 32Bit data read and write. */
        SEMC_SDRAMReadWrite32Bit();
        /* 16Bit data read and write. */
        SEMC_SDRAMReadWrite16Bit();
        /* 8Bit data read and write. */
        SEMC_SDRAMReadWrite8Bit();
...
}

 Please feel free to share with me if there are any further details.