IMXRT1172 boot time around 2 seconds

[kotalamit]

Hi,

We are using IMXRT1172 microcontroller with XIP and External SDRAM. In our application design we have an External Watchdog which needs to be kicked within 1.2 Secs to prevent a reset signal. 

The issue we are facing is the IMXRT is taking too long of time i.e. 2 secs to start execution from main, where the first action to be done in main is to initialize the watchdog refresh GPIO and send a signal transition, but on measuring the signal over DSO it is observed that the first edge of low to high appears after 2 secs of the power up signal. Below is the abstract of the main init code;

int main(void)
{

Initialize_wdtRst();
GPIO_PinWrite(GPIO3,31,1);  //WDT Refresh GPIO [The time to reach here is 2 secs]

/* Init board hardware. */
BOARD_ConfigMPU();
GPIO_PinWrite(GPIO3,31,0); //WDT Refresh GPIO
BOARD_InitPins();

GPIO_PinWrite(GPIO3,31,1); //WDT Refresh GPIO

BOARD_BootClockRUN();
BOARD_InitDebugConsole();

while(1)

{

//Some Code

}

}


Similarly, I have tried to test the littlefs code for reset timing, it was observed to be 20ms. 

Any help to understand why the timing difference between the two codes on the same hardware??


Regards,
Amit K

[nxf42461]

Hi Amit,

One small check at our end, Can you try adding this function on the ResetISR rather than on the Main, Because generally perform a Flash to SDRAM copy of the data region whose timings can vary on every project.

We have a weak implementation of the SystemHook function available on all of our workspace, Which can be used for our trials here.

Below snap-shot for further reference. 

/* ----------------------------------------------------------------------------

-- SystemInitHook()

---------------------------------------------------------------------------- */

__attribute__ ((weak)) void SystemInitHook (void) {

/* Void implementation of the weak function. */

}

Do help check and let me know for any further information required. 

With Regards,

Nikhil Ullal

[kotalamit]

Hi @diego_charles 

Following up to know if you have any further inputs based on the last shared information.

Regards,

Amit Kotal

[diego_charles]

Hi  @kotalamit 

Thanks for the detailed reply! 

I see that the reset_b  is released  in the order of tens of milliseconds. I got more points to check:

1. Can you measure the reset_b against the last power rail being booted?
2. If you assert reset_b the boot is again of two seconds, or this appears after a power cycle?
3. Do you have any RT internal watchdog being set, debug probe attached, specific fuse settings,  secondary bootloader, or secure boot settings? If this a sensitive question, feel free to reply in the internal ticket as explained below.

Lastly,I want to take a look at your schematic, I created a internal ticket for this, if you could share over that portal it could be good. Please check you email inbox for that case. 

All the best,

Diego

[kotalamit]

Hi @diego_charles,

Thanks for the reply.

Following below are the answers to your queries;

1. Can you measure the reset_b against the last power rail being booted?
   
   1. A. The reset timing remains the same as 1.5 Secs approx.
2. If you assert reset_b the boot is again of two seconds, or this appears after a power cycle?
   1. A. If we physically assert the reset_b, still the timing delay is 1.5 secs.
3. Do you have any RT internal watchdog being set, debug probe attached, specific fuse settings,  secondary bootloader, or secure boot settings? If this a sensitive question, feel free to reply in the internal ticket as explained below.
   1. A. We are not using Internal watchdog, no probe attached, no fuse setting other than default factory, no secondary bootloader or secure boot settings. 

I have also added the appropriate reply for the the internal ticket.

Thanks and Regards,

Amit Kotal

[diego_charles]

Thanks for your response @kotalamit 

Lets continue the follow up of this issue  with the ticket! 

All the best, 

Diego 

[diego_charles]

Hi @kotalamit 

I hope you are doing great! 

Could you let me know what it is inside the Initialize_wdtRst() function? Is there any code looping in a while, waiting for any flag or value to be set? 

Are you using an external reset IC? Generally, this IC is used to de-assert the reset signal after all the power rails have booted. For example, in our RT1060 EVK, the reset monitoring chip de-asserts the reset_b line after 200 mS, on a POR reset, which is enougth time for all the rails to be booted.

Anyway,  for trouble shooting this : I recommend measuring how much time does it takes the reset pin to be de-asserted, even if you are not using this reset IC. Measure against the first rail booted, I think it is VDD_SNVS_IN . Please share your results. 

All the best,

Diego

[kotalamit]

Hi Diego,

Thanks for the prompt reply, as requested following below is the function definition

/*
* Configure the WDT RST Gpio On Boot Up
*/
void Initialize_wdtRst(void)
{
/* GPIO configuration of WDT_RST on GPIO_AD_32 (pin K16) */
gpio_pin_config_t WDT_RST_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_32 (pin K16) */
GPIO_PinInit(GPIO3, 31U, &WDT_RST_config);

IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31, /* GPIO_AD_32 is configured as GPIO_MUX3_IO31 */
0U);

IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31, /* GPIO_AD_32 PAD functional properties : */
0x0EU); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Enable
Pull Up / Down Config. Field: Weak pull up
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}

Following below is the signal where CH1(Yellow) is the VDD_SNVS_IN and CH2(Green) is the RST signal.

CH 1(Yellow) => VDD_SNVS_IN and CH2 (Green) => uC RST

Additonally below is the signal showing the WDT Refresh Signal Latency vs WDT power up time. CH1(Yellow) => WDT Refresh Pin and CH2 (Green) => WDT VDD

Appreciate you inputs.

Regards,

Amit Kotal