IMXRT1052 JTAG, PHY.MAC MII and BOOT pin multiplexing

[debug]

Designing a board, the ask is to connect to a PHY using MII. For example the DP83640 but this could be any MII PHY.  All examples found use RMII. These are some of the issues:

1. Pin multiplexing BOOT/JTAG/RXDATA/TXDATA

Some PHY pins are multiplexed with JTAG and MII interface.

1A  JMOD & RX_DATA3 (RMII mode)

 Pull ups/downs on the RXD3/JTAG pin or via jumper.? How about signal integrity for these two options ?

1B. ETH TX DATA 2/3  & BOOT pins
 Just add a pull up to force to 1, if R2/R3 not installed, BOOT0/BOOT1=0?

1C. JTAG_TMS/SWDIO/ENET_RX_CLK , ENET_RXDATA2/JTDI  & ENET_COL/JTAG_TRSTBT
The same as question 1a but now for the pins in yellow. Connect the signal together or via a 3 way jumper to select the signal ? Here the concern is also signal integrity for long traces to JTAG and the PHY.

1D. JTAG_TRSTB

Should it be connector to system RESET signal or only to the JTAG Reset pin ?

2.  RX_DV

The PHY has a separate RX_DV output. In RMII DV is mixed with the CRS on the CRS pin as CRS_DV.

2A. DV and CRS signals

In MII mode the DV signal is a physical separated one from the CRS output. How to connect the PHY RX_DV pin to the MAC . RX_DV MII is specified in IEEE 802.3 Clause 22:

RX_DV is asserted when the preamble is detected, and it is deasserted at the end of the frame, see Clause 22.2.2.7 for details:

RX_DV (Receive Data Valid) is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on the RXD<3:0> bundle and that the data on RXD<3:0> is synchronous to RX_CLK. RX_DV shall transition synchronously with respect to the RX_CLK. RX_DV shall remain asserted continuously from the first recovered nibble of the frame through the final recovered nibble and shall be negated prior to the first RX_CLK that follows the final nibble. In order for a received frame to be correctly interpreted by the Reconciliation sublayer and the MAC sublayer, RX_DV must encompass the frame, starting no later than the Start Frame Delimiter (SFD) and excluding any End-of-Frame delimiter.

t looks like RX_RV from the MAC can be connected to RX_EN at the MAC ?

Per the RMII spec RX_DV is multiplexed on RX_CRS, but NPX spec states RX_EN is used in both RMII/RMII, It seems the reference guide is incorrect and should ONLY list "RMII" for ENET_RX_EN ?

The reference guide  states the pin is defined as "RMII_CRS_DV" when RMII mode register is set. Where is the "RMII_CRS_DV" pin ? Does this pin function as CRS_DV or should ENET_RX_CRS pin be used for the CRS_DV function or both output the same signal ?  For ENET_CRS it states: This signal is present on the RMII_CRS_DV pin."  RMII_ CRS_DV pin is not listed in the spec as a pin.

3. RX_ER

Per RMII spec, RX_ER is only required in MII mode. but the reference guide list both used in RMII and MII mode.

[jingpan]

Hi @debug ,

1A. RT1050 support SWD by default. To support JTAG, you must program eFuse. So, I think you design is fine.

1B. BOOT_MODE1 and BOOT_MODE0 each have on-chip pull-down devices with a nominal value of 100 kΩ, a projected minimum of 60 kΩ, and a projected maximum of 140 kΩ. But I think they are too big. I prefer to use pullup/pulldown resistor.

1C. Yes

2.  It uses the RX_EN instead of the MII_RXDV.

3. Yes

Regards,

Jing

[debug]

1A/1C. Which solution should be used, the upper or lower solution diagram  ?

1B. So the solution  would be to have a 10K pull up and down resistor on BOOT pins?  Since these pins are shared with ETHERNET data, and  if pulled high,would this cause issues so signal integrity of the Ethernet signals ?

2. The particular PHY has separate RX_DV (MII) and RX_CRS/CRS_DV (MII/RMII) output. it has no RX_EN output. To which signal should these connect on the 6ULL ?  I have routed PHY RX_DV to pin C12 and  PHY RX_CRS_DV to pin G31.   Would that work when either in RMII or MII mode ?

3. Does that confirm the manual incorrectly lists RMII mode for RX_ER ?

Thank you so much.