FlexSPI Nor Config Structure Clarification

[Ykciv]

Im using HyperFlash(S26HL01GT) as boot memory with IMXRT1176 Controller.

We already modified the flexspi_nor_config structure for boot configuration and its working.

We need to configure the HyperFlash Drive Strength and its possible with LUT Table, Command and device config update. But im not sure about the exact configurations needed to achieve that.

Is there any application note which explains the configurations needed for different Memory chips and LUT sequence?

[Ykciv]

Hi.

Any info about the LUT Sequence?

[jay_heng]

The content of LUT sequence is up to Flash chip. we need to set LUT according to Flash command description

I have a blog on LUT topic, it is written in Chinese

从头开始认识i.MXRT启动头FDCB里的lookupTable

[Ykciv]

I understood but what i dont get is, How it links with the internal execution.

For example, Read Sequence is present in index zero of LUT table in the example you shared. If I place the Read Sequence at index 10 will it work?

How controller recognizes which is read sequence, Erase and other config sequences?

Where are we specifying these commands or is there any preconditions like Read should always start from index zero like that?

[Ykciv]

Thanks for the response. I'll check the configurations.

Is there any brief explaination about deviceMode and configCmd parameters and how it links with LUT?

[jay_heng]

There is not detailed explanation on this, but you can refer to attached example file for device cfg usage. 

In RT595, we use device cfg to enable OPI DDR mode for MX25UM51345

[Ykciv]

Hi,

I checked the config file, in that file if I update the LUT table configuration alone for my hyperflash config is it enough?

How the LUT index is assigned for the read command and device config command in the shared file?

I need to modify the file for my application, Without understanding how it works, it will be difficult for me to update. Can you please give short explanation for LUT index mapping alone?