CPU occasionally hangs on writes to FlexSPI when Instruction Cache is enabled.

[dciliske]

I've got a intermediate R&D board using 1061 that seems to be behaving in the oddest way.

Basically the situation is a follows:

1. The triggering code is located in a HyperRAM connected to the FlexSPI.
2. There is an active Ethernet MAC who's buffers live in OCRAM. 
3. The Descriptor Rings for the MAC live in DTCM.

Occasionally, when an Ethernet RX interrupt occurs, the CPU will hang with the Program counter pointing at a store instruction. At the time of the hang the registers used by the store would cause a write to be made to the HyperRAM on the FlexSPI. However, if the Instruction Cache is _disabled_ it appears that the hang does not occur.

Anyone have any thoughts here?

[Hui_Ma]

Hi,

We have answered a quite similar case, please check here for the detailed info.

The conclusion is to place Ethernet data buffer at non-cachable memory range.

In previous case, the root cause is: When ENET and core as two masters to access the same memory range in OCRAM, in fact both master will access the cache instead of access the OCRAM memory range directly. There could exists the issue when cached data is different with actual data in OCRAM. So, it need to do cache maintainance during actual application.

The similar issue also could happen with USB application, we also recommend customer to place USB data buffer at non-cacheable memory range.

Thanks for the attention.

best regards,

Mike

[dciliske]

The issue isn't the ethernet data buffers; I have the Data cache disabled.

Can you provide any information regarding AXI Wrap bursts for LineFills and how they interact with the FLEXSPI AHB RX sequences? As this appears to be related to the Instruction Cache this seems to be potentially relevant. Are WRAP bursts translated to INCR bursts by the time the FLEXSPI executes the read?

[Hui_Ma]

Hi,

I find below info for your reference:

Wish it helps.

Mike