what's the reletion of pll and phy pll in imx8mm dsi

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what's the reletion of pll and phy pll in imx8mm dsi

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jiangyaqiang
Contributor III

HI  :

      I found that , there is two descriptions about pll in imx8mm dsi:

pastedImage_1.png

pastedImage_2.png

what's the relation of them ? The "DPHY PLL" Fout max is 750M only, but PLL up to 2.1G.

And in linux-4.14.78, if DSI is connected to a panel, the PMS is hard code to 0x4210(In this setting , the output of DSI clock is 445.5Mhz), what should I set if panel's pix clock is 148.5Mhz (I have tried function sec_mipi_dsim_get_pms(dsim->bit_clk) in 4.14.78, the DIS output clock is the same 445.5Mhz)?

Best 

Regards

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nxf54947
NXP TechSupport
NXP TechSupport

Hello jiangyaqiang‌,

Sorry for my late response. I was  corroborating the following the PMS settings and the phy clock with our application engineers.

1.The PMS value is decomposed in the following way:

0x4210 = > 0b10  0001000010  000  =>  P:2 M:66 S : 0  =>  891M , bigger than 792M , so it can work for 1080p panel.

2. The  phy clock is computed as shown below:

 

phy clock = pixel clk * bpp/ lanes. = 27M * M/(P * 2^S)

3. The 4.14.98 kernel release incorporates a PMS calculation function. You can merge it with 4.14.78 release for a special pixel clock. If you need more information on this, please raise a ticket into our internal system and mention me. The following link will show you how to proceed with this inquiry.

How to submit a new question for NXP Support

Best regards,

Ruben

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jiangyaqiang
Contributor III

HI Ruben:

  Thanks.

   But, the PMS_M starts at the 4bits.

   So,  0x4210 = > 0b10  000100001  0000  =>  P:2 M:33 S : 0  => 445.5M

   I reference to iMX_8M_Mini_RM_RevB.pdf, is that any update about it ? or anything I have missed unstand ?

  pastedImage_1.png

pastedImage_2.png

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nxf54947
NXP TechSupport
NXP TechSupport

Hello jiangyaqiang‌,

 From DSI bridge's drivers code, you can see that the value of the PMS divider are obtained tas shown below:

 

 root/drivers/gpu/drm/bridge/sec-dsim.c. line 207:

#define PLLCTRL_SET_PMS(x)  REG_PUT(x, 19,  1)   #define PLLCTRL_SET_P(x)  REG_PUT(x, 18, 13)   #define PLLCTRL_SET_M(x)  REG_PUT(x, 12,  3)   #define PLLCTRL_SET_S(x)  REG_PUT(x,  2,  0)

So, under this perspective, the LSB bit of M is the 4th bit of the pms value( 0x4210 ). According to this, several bitclocks can be obtained using the pms values of this structure:

 Line 386:

static const struct dsim_pll_pms pll_pms[] = { { DSIM_PLL_PMS(891000, 1, 66, 1), }, { DSIM_PLL_PMS(890112, 1, 66, 1), }, { DSIM_PLL_PMS(594000, 3, 66, 0), }, { DSIM_PLL_PMS(593408, 3, 66, 0), }, { DSIM_PLL_PMS(445500, 1, 66, 2), }, { DSIM_PLL_PMS(445056, 1, 66, 2), }, { DSIM_PLL_PMS(324000, 3, 72, 1), }, { DSIM_PLL_PMS(324324, 3, 72, 1), }, { DSIM_PLL_PMS(162000, 3, 72, 2), }, { DSIM_PLL_PMS(162162, 3, 72, 2), },}

For example, the first attribute indicates that 891MHz (represented in KHz) can be obtained by setting p=1; m= 66 and s= 1. Please consider that the PLLPMS needs values restricted within a range.

I hope this helps.

Ruben

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nxf54947
NXP TechSupport
NXP TechSupport

Hello jiangyaqiang‌,

The DPHY PLL relies on a PLL source in order to generate its Fout. In regarding the pixel clock configuration, I think that the following post will be an useful reference for you:

Setting i.MX8M Mini and Nano MIPI-DPHY Clock

I hope that the information provided was of any help!

Regards

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jiangyaqiang
Contributor III

HI Ruben Charles:

Thanks for your help.

I got one more question. From the linker you provide, the bit_clk=792Mhz, but I found the in source code(drivers/gpu/drm/bridge/sec-dsim.c kernel4.14.78 )dsim->pms = 0x4210 when there is a panel connected to the bridge. So, the Fout of the PLL will be p=2 m=0x21=33 s=0 Fout=27M*33/(2*2^0)=445.5M, it doesn't match 1080p60 OLED display RM67191's bitclk. Any thing I misunderstand ?

One more thing, in IMX8MQ, there is a DDR mode in DSI, that means, then the DSI clock will be half of bit_clk(pll Fout). Does IMX8M mini have DDR mode ?

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nxf54947
NXP TechSupport
NXP TechSupport

Hello jiangyaqiang‌,


Sorry for my delayed answer,

Just to let you know that I am still checking why Fout calcualation for the PLL driver differs from the 792 MHz value of the RM67191 display.  Could you let me know if you have experienced any issues with the DSIM driver yet?

Please allow me to inquire our application engineers with respect to the the availabity of DSI's module DDR mode . I will be replying on this post as soon as I get more information.

Regards, 

Ruben

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jiangyaqiang
Contributor III

HI Ruben Charles:

         Actually, I'm integrating a TI dsi to lvds module(sn65dsi84) to imx8mm. It successes with lvds clock close to or lower then 74.25M, fails at 1080P/60(mipi clock should be 74.25*2*6). 

        And about DDR module of DSI clock, it's the specification in MIPI DSI electrical of D-PHY layer. 

But I found that the Fout of PLL equal to IMX8MM DSI clock. I must misunderstand something. So I want to find out the relationship between two PLL and the DSI output clock.

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nxf54947
NXP TechSupport
NXP TechSupport

Hello jiangyaqiang‌,

My apologies for my delayed reply.

You may want to follow the panel specifications of the sn65dsi84 for pixel clock and timing. I think that's the reason of the difference between the computed bit clock, the RM67191 has a different pixel clock.   I've found some other community posts that might be helpful for you:

How to set up DSI D-PHY speed for low resolution panel?
IMX8M MIPI DSI to LVDS Bridge(SN65DSI84)
LVDS no image using sn65dsi84

I hope that the information provided was of any help!

Regards,

Ruben

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jiangyaqiang
Contributor III

HI Ruben Charles:

Thanks , But the link is for imx8mq, the clock setting for imx8mq is no problem , the problem happen in imx8mm.

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