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How to set up DSI D-PHY speed for low resolution panel?

Question asked by Oliver Kuo on Apr 16, 2019
Latest reply on Apr 16, 2019 by Oliver Kuo

Hi all,

 

I'm working on our i.MX8MQ custom board with DSI-LVDS bridge (Ti SN65DSI84) and trying to enable a 1024*768@60 LVDS panel, the BSP is Android P900_100.

DSI driver seems not able to work out usable CM/CN/CO values for DPHY PLL setting.

[ 2.413670] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* Cannot setup PHY for mode: 1024x600 @50400 kHz
[ 2.413676] nwl_dsi-imx mipi_dsi@30A00000: [drm:imx_nwl_try_phy_speed] *ERROR* PHY_REF clk: 27000000, bit clk: 403200000

I attached my dts file and log, timing table of panel is below.

static const struct display_timing sn65_default_timing = {
.pixelclock = { 44400000, 50400000, 65200000 },
.hactive = { 1024, 1024, 1024 },
.hfront_porch = { 304, 320, 338 },
.hsync_len = { 0, 0, 0 },
.hback_porch = { 0, 0, 0 },
.vactive = { 600, 600, 600 },
.vfront_porch = { 12, 25, 38 },
.vsync_len = { 0, 0, 0 },
.vback_porch = { 0, 0, 0 },

.flags = DISPLAY_FLAGS_HSYNC_HIGH |
DISPLAY_FLAGS_VSYNC_HIGH |
DISPLAY_FLAGS_DE_HIGH |
DISPLAY_FLAGS_PIXDATA_NEGEDGE,

}

The phyref_rates[] only defined 3 clock rates, if this is fixed and unchangeable, it looks like impossible to work out usable CM/CN/CO values!?

/* Possible valid PHY reference clock rates*/
u32 phyref_rates[] = {
24000000,
25000000,
27000000,
};

Anyone can help?

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