u-boot VDD_SOC_CAP, VDD_PU_CAP

[douglasbolton]

In the i.mx6 6Dual/6Quad Automotive and Infotainment Applications Processors datasheet rev 2.3 (page 21) it states that -

"VDD_SOC_CAP and VDD_PU_CAP must be equal."

However the latest version of i.mx6 u-boot has these voltages set to 1.2 volts and 1.15 volts.

I have also read that you can turn off the VDDPU_CAP ldo if VPU and GPU are not used.

Is the datasheet correct ?

Thanks Doug.

[douglasbolton]

Thanks Yongcai

[AnsonHuang]

The latest imx6 uboot has VDDSOC_CAP set to 1.2V and VDDPU_CAP shut off. The requirement is that if they are both on, their voltage should same, below is the uboot code:

1079         /* Need to power down xPU in GPC before turn off PU LDO */

1080         val = readl(GPC_BASE_ADDR + GPC_PGC_GPU_PGCR_OFFSET);

1081         writel(val | 0x1, GPC_BASE_ADDR + GPC_PGC_GPU_PGCR_OFFSET);

1082  

1083         val = readl(GPC_BASE_ADDR + GPC_CNTR_OFFSET);

1084         writel(val | 0x1, GPC_BASE_ADDR + GPC_CNTR_OFFSET);

1085         while (readl(GPC_BASE_ADDR + GPC_CNTR_OFFSET) & 0x1)

1086                 ;       

1087  

1088         /* Increase the VDDSOC to 1.2V and disable VDDPU */

1089         val = REG_RD(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE);

1090         val &= ~BM_ANADIG_REG_CORE_REG2_TRG;

1091         val &= ~BM_ANADIG_REG_CORE_REG1_TRG;

1092         val |= BF_ANADIG_REG_CORE_REG2_TRG(0x14);

1093         REG_WR(ANATOP_BASE_ADDR, HW_ANADIG_REG_CORE, val);

[douglasbolton]

Thank you for that answer, it was very helpful. I was using a previous version of u-boot !!!

I have just updated to u-boot imx_v2013.04_3.5.7_1.0.0_alpha but it doesn't match the code snippet you supplied. Can you tell me what is the latest version I should be using.

Thanks

Doug

[AnsonHuang · Accepted solution]

Hi,

     The code I pasted is imx_v2009.08, for imx_v2013.04, the code should be as below, you can use either of them according to your need of uboot.

arch/arm/cpu/armv7/mx6/soc.c:

328 static void imx_set_vddpu_power_down(void)

329 {

330         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;

331         u32 val;

332

333         /* need to power down xPU in GPC before turn off PU LDO */

334         val = readl(GPC_BASE_ADDR + 0x260);

335         writel(val | 0x1, GPC_BASE_ADDR + 0x260);

336

337         val = readl(GPC_BASE_ADDR + 0x0);

338         writel(val | 0x1, GPC_BASE_ADDR + 0x0);

339         while (readl(GPC_BASE_ADDR + 0x0) & 0x1)

340                 ;

341

342         /* disable VDDPU */

343         val = 0x3e00;

344         writel(val, &anatop->reg_core_clr);

345 }

346

347 static void imx_set_pcie_phy_power_down(void)

348 {

349         u32 val;

350

351         val = readl(IOMUXC_BASE_ADDR + 0x4);

352         val |= 0x1 << 18;

353         writel(val, IOMUXC_BASE_ADDR + 0x4);

354 }

355

356 int arch_cpu_init(void)

357 {

358         init_aips();

359         set_vddsoc(1200);       /* Set VDDSOC to 1.2V */

360

361         imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

362

363         imx_reset_pfd();

364         imx_set_pcie_phy_power_down();

365         imx_set_vddpu_power_down();

366

367 #ifdef CONFIG_APBH_DMA

368         /* Start APBH DMA */

369         mxs_dma_init();

370 #endif

371

372         return 0;

373 }