imx6D 内核linux4.15 板子连一块mipi 720*1280 的屏和lcd 800*600的屏,当把内容输出到LCD时就出现了mxc_mipi_dsi 21e0000.mipi: mipi_dsi IRQ status0:0x0, status1:0x80
然后就崩溃了!!!!!
Solved! Go to Solution.
For example:
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
我尝试了下是可以的,真的真的非常感谢
我用的就是不同的ipu
Clock is the key point of your issue.
大概需要在那些地方做设置
杭州笃远
李俊
lij@dofartech.com
0571-28833531
杭州古荡街道毛家桥路中天MCC 2#210
For example:
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
我尝试下 非常感谢
杭州笃远
李俊
lij@dofartech.com
0571-28833531
杭州古荡街道毛家桥路中天MCC 2#210
You should assign different IPU DI port to LCD and MIPI Display. And you should also assign different clock source for the two displays.
For example in device tree for different disp_id:
lcd@0 {
compatible = "fsl,lcd";
ipu_id = <0>;
disp_id = <0>;
default_ifmt = "RGB565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1>;
status = "okay";
};
&mipi_dsi {
dev_id = <0>;
disp_id = <1>;
lcd_panel = "TRULY-WVGA";
disp-power-on-supply = <®_mipi_dsi_pwr_on>;
resets = <&mipi_dsi_reset>;
status = "okay";
};
For clock source, it is in file arch\arm\mach-imx\clk-imx6q.c, function imx6q_clocks_init():
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
The default setting used the same clock source, PLL5. So when the second display was enabled, it will impact the first display.