Hi There,
I'm working on a imx8mm evaluation board, running BSP 5.4-zeus, BB_VERSION = "1.44.0", linux kernel 5.4.47.
I'm trying to set clock source to the GPT.
According to "i.MX 8M Mini Applications Processor Reference Manual", page 280, Table 5-1, the maximum clock frequency that can be used is 100MHz.
According to page 3855, 12.1.5.1, GPT Control Register, the clock source can be determined by setting bits 8-6 during the setup procedure of the GPT.
By editing the GPT driver, drivers/clocksource/timer-imx-gpt.c I tried all the variants, but the maximum clock frequency I got is 24MHz.
Please help me to configure that clock source to get at least 66MHz.
Thanks,
Nir.
Hi Igor,
Thanks for your reply.
It looks like the clock driver, drivers/clk/imx/clk-imx8mm.c, defines the available clock sources for the GPT module in line 301:
301 static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
302 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
This definition complies perfectly with Table 5-1.
However, the clock source is determined by bits 6-8 in the GPT control register, 12.1.5.1
How exactly are these 3 bits mapped to the structure imx8mm_gpt1_sels[]?
How can I figure out what is the frequency of "High Frequency Reference Clock (ipg_clk_highfreq)", or "Peripheral Clock (ipg_clk)"?
As I stated, any combination of bits I'm trying yields a maximum frequency of 24MHz. (I'm setting the prescaler to 1).
Can you please direct me how to set sys_pll2_100m as the clock source instead of osc_24m?
Thanks a lot,
Nir.
Hi Nir
one can try to debug it using AN4553 Using Open Source Debugging Tools for Linux on i.MX Processors
https://www.nxp.com/docs/en/application-note/AN4553.pdf
Also I sent additional patch by mail, however for complete solution suggest to proceed with help of
https://contact.nxp.com/new-prof-svcs-sw-tech
Best regards
igor
Hi Nir
one can check clock driver
Linux common clock framework documentation
https://www.kernel.org/doc/Documentation/clk.txt
www.linuxsecrets.com/elinux-wiki/images/b/b8/Elc2013_Clement.pdf
example:
Best regards
igor
Hi Igor,
Thanks for your reply.
It looks like the clock driver, drivers/clk/imx/clk-imx8mm.c, defines the available clock sources for the GPT module in line 301:
301 static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m",
302 "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" };
This definition complies perfectly with Table 5-1.
However, the clock source is determined by bits 6-8 in the GPT control register, 12.1.5.1
How exactly are these 3 bits mapped to the structure imx8mm_gpt1_sels[]?
How can I figure out what is the frequency of "High Frequency Reference Clock (ipg_clk_highfreq)", or "Peripheral Clock (ipg_clk)"?
As I stated, any combination of bits I'm trying yields a maximum frequency of 24MHz. (I'm setting the prescaler to 1).
Can you please direct me how to set sys_pll2_100m as the clock source instead of osc_24m?
Thanks a lot,
Nir.