imx6sx fec RMII ENET1_REF_CLK1

[peterbärtsch]

Hello

I want to configure the ENET1_TX_CLK pin as ENET1_REF_CLK1 with 50Mhz for the phy. In u-boot it works. But not in kernel.

DTS config:

&fec1 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_enet1>;

    pinctrl-assert-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>, <&gpio1 10 GPIO_ACTIVE_LOW>;

    phy-mode = "rmii";

    status = "okay";

};

pinctrl_enet1: enet1grp {

    fsl,pins = <

        MX6SX_PAD_ENET1_MDIO__ENET1_MDIO    0xa0b1

        MX6SX_PAD_ENET1_MDC__ENET1_MDC        0xa0b1

        MX6SX_PAD_ENET1_CRS__ENET1_CRS         0xa0b1

        MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x0051

        MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0    0xa0b1

        MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1    0xa0b1

        MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1

        MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0    0x3081

        MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1    0x3081

    >;

};

I change in the mach-imx6sx.c file IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK to "1"

static void __init imx6sx_enet_clk_sel(void)

{

    struct regmap *gpr;

    gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");

    if (!IS_ERR(gpr)) {

        regmap_update_bits(gpr, IOMUXC_GPR1,

                   IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);

        regmap_update_bits(gpr, IOMUXC_GPR1,

                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 1);

    } else {

        pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");

    }

}

What should I do?

Peter

[alejandrolozan1]

Hi,

Just to double check, if you configure the pin in uboot but you do not try to reconfigure it in Linux, Does it work?

Have you used the memtool application found in the  /unit_tests folder? that can help to check the register configurations of the IOMUXC. Please use that and check that the IOMUXC is configured correctly.

Best Regards,

Alejandro

[peterbärtsch · Accepted solution]

Hi

Yes it do :smileylaugh: I found the problems with the devregs tool. Here my patch. May be helpful for someone.

Index: kernel-source/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

===================================================================

--- kernel-source.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h    2015-12-05 09:54:09.201580469 +0100

+++ kernel-source/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h    2015-12-05 09:54:15.237580459 +0100

@@ -397,9 +397,9 @@

#define IMX6SX_GPR1_VADC_SW_RST_MASK            (0x1 << 19)

#define IMX6SX_GPR1_VADC_SW_RST_RESET            (0x1 << 19)

#define IMX6SX_GPR1_VADC_SW_RST_RELEASE            (0x0 << 19)

-#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK      (0x3 << 13)

-#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK      (0x3 << 17)

-#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT       (0x3 << 13)

+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK          (0x1 << 13)

+#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK          (0x1 << 17)

+#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT           (0x1 << 13)

#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK            (0x1 << 26)

#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT        (26)

Index: kernel-source/arch/arm/mach-imx/mach-imx6sx.c

===================================================================

--- kernel-source.orig/arch/arm/mach-imx/mach-imx6sx.c    2015-12-05 09:53:51.685580497 +0100

+++ kernel-source/arch/arm/mach-imx/mach-imx6sx.c    2015-12-05 10:08:39.025579056 +0100

@@ -211,7 +211,7 @@

         regmap_update_bits(gpr, IOMUXC_GPR1,

                    IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);

         regmap_update_bits(gpr, IOMUXC_GPR1,

-                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);

+                   IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK);

     } else {

         pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");

     }

Index: kernel-source/arch/arm/mach-imx/clk-imx6sx.c

===================================================================

--- kernel-source.orig/arch/arm/mach-imx/clk-imx6sx.c    2015-12-05 09:53:51.661580497 +0100

+++ kernel-source/arch/arm/mach-imx/clk-imx6sx.c    2015-12-05 09:54:15.237580459 +0100

@@ -615,8 +615,8 @@

     imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);

     imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);

     imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);

-    imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);

-    imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);

+    imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 50000000);

+    imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 50000000);

     /* Audio clocks */

     imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);

Index: kernel-source/arch/arm/boot/dts/imx6sx-pinfunc.h

===================================================================

--- kernel-source.orig/arch/arm/boot/dts/imx6sx-pinfunc.h    2015-12-05 09:53:51.409580498 +0100

+++ kernel-source/arch/arm/boot/dts/imx6sx-pinfunc.h    2015-12-05 09:54:15.237580459 +0100

@@ -316,7 +316,7 @@

#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35                     0x008C 0x03D4 0x0000 0x8 0x0

#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29                0x008C 0x03D4 0x0000 0x9 0x0

#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK                      0x0090 0x03D8 0x0000 0x0 0x0

-#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x0090 0x03D8 0x0760 0x1 0x1

+#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                    0x0090 0x03D8 0x0760 0x11 0x1

#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD                   0x0090 0x03D8 0x0644 0x2 0x1

#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B                       0x0090 0x03D8 0x0000 0x3 0x0

#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK                      0x0090 0x03D8 0x0000 0x4 0x0