imx6q suspend/resume issue

[AndyHo]

Hi,

We have a imx6quad(MCIMX6Q5EYM10AD,1GHz) customize board what is designed refer to IMX6Q-SDP, the BSP we use are android 4.4.3 and 5.0 source from freescale, both original BSPs can suspend/resume successfully on IMX6Q-SDP.

We modify the BSP for our customized board, change the DDR3->LPDDR2 ( 1GB (2 x SK-Hynix Lpddr2 x32,8Gb), boot config as lpddr2 2x32), ddr stress passed ), some gpios ( all configured and controlled), PMIC(MPF0100F0->F3) & its VSWx/GENs voltage, we have done measured all power domain and related cpu->pmic signals, no difference from IMX6Q-SDP. The system can suspend but fail to resume, the system will be reset when we push power button to resume system and we always see the cause is WDOG.

From the BSP and Reference Manual, a timeout watchdog is implemented and it's suspend during system sleep, since our system can enter suspend and the watchdog is never triggered during android runs or system in suspend mode.I think the root cause may not be watchdog timeout, but how a watchdog is set becides timeout and who can trigger watchdog during suspend? Please note that the powerdown bit is set in watchdog.

So we hope anyone can help/hint us to debug the issue: HOW the system resume become watchdog reset?

Thank you.

======================suspend/reusme log========================

Starting kernel ...

Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpu
Initializing cgroup subsys cpuacct
Linux version 3.10.53-88204-g4f0dd92-dirty (android@ubuntu) (gcc version 4.6.x-google 20120106 (prerelease) (GCC) ) #9 SMP PREEMPT M
on Nov 16 19:57:00 PST 2015
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Freescale i.MX6 Quad/DualLite (Device Tree), model: Freescale i.MX6 Quad SABRE Smart Device Board
cma: CMA: reserved 384 MiB at 18000000
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 8 pages/cpu @82205000 s9728 r8192 d14848 u32768
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260864
Kernel command line: console=ttymxc4,115200 init=/init video=mxcfb0:dev=lcd,RGB666,bpp=24 video=mxcfb1:off video=mxcfb2:off video=mx
cfb3:off vmalloc=400M androidboot.console=ttymxc4 consoleblank=0 androidboot.hardware=freescale cma=384M androidboot.selinux=disable
d androidboot.dm_verity=disabled no_console_suspend=1 androidboot.serialno=1d1751d4e31698d2
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 512MB 447MB 64MB = 1023MB total
Memory: 627668k/627668k available, 420908k reserved, 523264K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xa0800000 - 0xff000000   (1512 MB)
    lowmem  : 0x80000000 - 0xa0000000   ( 512 MB)
    pkmap   : 0x7fe00000 - 0x80000000   (   2 MB)
    modules : 0x7f000000 - 0x7fe00000   (  14 MB)
      .text : 0x80008000 - 0x80e7a498   (14794 kB)
      .init : 0x80e7b000 - 0x80ed0600   ( 342 kB)
      .data : 0x80ed2000 - 0x80f56000   ( 528 kB)
       .bss : 0x80f56000 - 0x80feacf8   ( 596 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Preemptible hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1048576 B
imx_gpc_init done!
imx6_set_lpm
sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655ms
CPU identified as i.MX6Q, silicon rev 1.5
Console: colour dummy device 80x30
Calibrating delay loop... 1581.05 BogoMIPS (lpj=7905280)
pid_max: default: 32768 minimum: 301
Security Framework initialized
SELinux:  Initializing.
Mount-cache hash table entries: 512
Initializing cgroup subsys debug
Initializing cgroup subsys freezer
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x807e2368 - 0x807e23c0
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU2: Booted secondary processor
CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
CPU3: Booted secondary processor
CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
Brought up 4 CPUs

.

.

.

.

lowmemorykiller: oom_adj 0 => oom_score_adj 0
lowmemorykiller: oom_adj 1 => oom_score_adj 58
lowmemorykiller: oom_adj 2 => oom_score_adj 117
lowmemorykiller: oom_adj 3 => oom_score_adj 176
lowmemorykiller: oom_adj 9 => oom_score_adj 529
lowmemorykiller: oom_adj 15 => oom_score_adj 1000
acc_open
acc_release
request_suspend_state: sleep (0->3) at 42170317671 (1970-01-01 00:00:40.291426338 UTC)
active wake lock PowerManagerService.Display
PM: suspend entry 1970-01-01 00:00:40.303337338 UTC
Freezing user space processes ... (elapsed 0.066 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
PM: suspend of devices complete after 62.504 msecs
PM: suspend devices took 0.070 seconds
PM: late suspend of devices complete after 0.425 msecs
PM: noirq suspend of devices complete after 0.539 msecs
Disabling non-boot CPUs ...
CPU1: shutdown
CPU2: shutdown
CPU3: shutdown

<---- Push Power button to resume ---->

U-Boot 2014.04-08648-g9d7bf9b-dirty (Nov 13 2015 - 01:41:57)

CPU:   Freescale i.MX6Q rev1.5 at 792 MHz
CPU:   Temperature 31 C, calibration data: 0x56c4e869
Reset cause: WDOG
Board: MX6-SabreSD
I2C:   ready
DRAM:  DRAM size 0x20000000
1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment

No panel detected: default to wvga-rgb
Display: wvga-rgb (800x480)
In:    serial
Out:   serial
Err:   serial

[gaun]

I am also facing the same issue. In my case I have a lpddr2 running at 200MHz and it passes the stress test. Do I need to change anything in lpddr2_freq_imx6.S? I am expecting it to work at frequencies set in the DCD file. Does it blindly change to 400MHz or something.

Which files should I start looking?

[AndyHo]

Hi Gautam,

The root cause of lpddr2 suspend issue is the implementation in pm_imx6.c and suspend.s, , because the code is for single channel and ddr3, so you can compare to the patch and see the difference,

Andy

[igorpadykov · Accepted solution]

Hi Andy

seems board just hangs then resets by wdog. One can check suspend/resume codes in

mx6_suspend.S, below some references for older kernels, since FSL BSPs do not support

i.MX6Q LPDDR2 configuration

i.MX6DL LPDDR2 Support for L3.0.35_4.0.0

http://www.technexion.com/support/download-center/edm/edm1-cf-imx6

Best regards

igor

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[AndyHo]

Hi Igor,

After modify some code refer to the patch you provide, the wdog resume reset issue is gone, thank you.

In our design, the LPDDR2 is working at 1066/528MHz ( 400MHz can't boot into kernel even ddr stress passed, don't know why), but the LPDDR2 related code is for 400MHz, I think maybe the do you have another patch for LPDDR2@1066/528 for dvfs or suspend/resume?

Best Regards,

Andy

[jiujinhong]

Hi Andy, can you look at my issue? My board can not work in DDR528.

Can you take a look at this post https://community.freescale.com/message/628232#comment-628232  ,latest discussion part?

[AndyHo]

Hi Igor,

Thank you very much for your information.
I will give it a try then post the result.

Best Regards,

Andy