imx6q pcie phy writel error

[liangjiang]

Our solution to using an external reference 100M for PCIe has three parts:

1. 1. Configure the CLK pins to accept a clock as input.
2. 2. Bypass the ENET PLL, using the CLK pins as the alternate source.
3. 3. Configure the PCIe PHY to accept a clock other than 125 MHz.

So i should set  PCIe PHY MPLL config: multiplier = 25, clkdiv2 = 0

but when i run at     writel(temp_wr_data, dbi_base + PHY_CTRL_R);   zhe system is die

static int pcie_phy_cr_cap_addr(int addr)

{

        u32 temp_wr_data;

        printk("jll   %s,%d\n",__func__,__LINE__);

        /* write addr */

        temp_wr_data = addr << PCIE_CR_CTL_DATA_LOC ;

        printk("jll  %s,%d\n",__func__,__LINE__);

        writel(temp_wr_data, dbi_base + PHY_CTRL_R);

~       ........

}      

Original Attachment has been moved to: pcie.c.zip

[Yuri]

Hello,

   Basically, there are several options for generating clock for i.MX6 PCIe module,

please look at PCIE_AXI_CLK_ROOT Figure 18-2 "Clock Tree" i.MX6DQ

Reference Manual. Note, i.MX6 PCIe module requires 125MHz clock  for normal

operation - all other clocks it produces internally - please refer to  section 18.5.1.3.6

"Ethernet PLL", it describes   Ref_PCIe =125 MHz.  Again, 100 MHz PCIe reference

clock is generated from this clock internally.

   The PCIe clock signal pair is not part of the PCIe PHY IP (assuming the CLK1N/P are used).

They are configured via  PMU_MISC1n register. 

  Also, please refer to the i.MX6 Datasheet  regarding CLK1 hardware specs.

Have a great day,
Yuri

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