Hi,
I'm investigating how to modify the qspi-onor-micron-n25q256a-config file to use with our custom board, which is based on the Sabre SoloX eval board.
The difference is we are using a single Flash chip attached to QSPI1 port, while the Sabre uses two Flash chips attached to the QSPI2 port.
In the config file, I see the following:
8000000 | /*sflash_A1_size=size in byte(hex)*/ |
0 | /*sflash_A2_size=size in byte(hex)*/ |
8000000 | /*sflash_B1_size=size in byte(hex)*/ |
0 | /*sflash_B2_size=size in byte(hex)*/ |
Since the Sabre uses QSPI2, I would have expected these entries to be on the A2 and B2 lines (not the A1, B1 lines)
So question is: do the lines above in the config file correspond to the QSPI ports?
If they do, what is the mapping?
If not, what do the lines represent? Just generic flash devices?
And of course, for my application with a single, 256Mbit device on QSPI1A port what should the lines above be changed to?
Also assuming I need to change the sflash_type to a 1. Correct?
Thanks,
bruce...
Hi Bruce
these fields do not select QSPI number, they define
generic flash map, divided equally for A and B ports,
note overall one qspi memory range is 256MB :
SFA1AD = qspin_base_address + sflash_A1_size;
SFA2AD = SFA1AD + sflash_A2_size;
SFB1AD = SFA2AD + sflash_B1_size;
SFB2AD = SFB1AD + sflash_B2_size;
sflash_type needs to be changed to a 1, correct.
Best regards
igor
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What is SFA1AD? The entry in the config file?
QSPI1 base addr = 0x6000_0000
so for system with a single 32MB Flash on QSPI1, the entry is 0x6200_0000 ?
yes QSPI1 base addr = 0x6000_0000,
SFA1AD is described in sect.51.13.23 Serial Flash A1 Top
Address (QuadSPIx_SFA1AD) i.MX6SX Reference Manual
http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf
~igor
Thanks Igor but the answer to my basic question is still unclear.
The entry in the config file for a single 32MB Flash device on QSPI1 should be 0x62000000 ??
sorry, what do you mean by "entry in the config file" exactly ?
One can use this default config file (mean sflash_xx) and it will work.
BOOT_CFG1[3] selects qspi1 or qspi2, sflash_xx define memory between
A and B ports: equally per 128MB (8000000).
As for other nor boot options (for example from spi or parallel nor),
there is no need to set flash size.
~igor