iMX8QXP LVDS dual channel with M4

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iMX8QXP LVDS dual channel with M4

383 次查看
mattiasecchiaro
Contributor I

Dear community,

I'm working on a project with iMX8QXP, where DPU and LVDS are managed by M4 core.

Is there a way to set LVDS0 in dual channel split mode using the MCUXpresso SDK?

And/or there is a software example about this?

Thanks.

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344 次查看
Sanket_Parekh
NXP TechSupport
NXP TechSupport

Hello @mattiasecchiaro 

I hope you are doing well.

->Yes, there is a register called tcon_CTRL, Whose field 0 & 1 is used for setting the channel mode.
->One can select the channel mode of any of the below three available modes.

00b - Single pixel mode. Both channels channel are active at full pixel clock. If the bitmap of both panels is the same, both panels are identical

01b - Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives display columns with even and 2nd one with odd index.

10b - Dual pixel mode. Both channels are active at half the pixel clock. 1st channel drives the left and 2nd on the right half of the display. 

Note: data_en is needed in this mode.

But there are no examples given that are using the respected register.

Thanks & Regards,
Sanket Parekh
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