Thank You @Bio_TICFSL for your reply.
Actually we have below test scenario,
1. iMX processor (Master 1 SPI) is communicating with IC1(Slave SPI).
2. We need to add one more master in between case 1. So that when Master 2 is communicating with IC1 slave, imx processor Master SPI is in tristate/IDLE/Disable but it should affect communication between additional master 2 and IC1 slave.
At a time only one master will be active.
When we are disabling master 1 iMX processir SPI then we are seeing that Master 2 is not able to communicate with slave IC1
(We need help to solve this.)
3. This master 1 is imx processor. SPI lines are shared between Master 1 Master 2 and Slave IC1.
4. When Master 2 is connected with Slave IC1 on another setup where imx processor is NOT present then SPI communication is working.
