iMX8M: meaning of CSI2RX_BIT_ERR?

[ensc]

Hello,

reference manual says

Is the content of this register persistent?   E.g. assuming two transfers where the first one has a bad CRC and the second one is ok.  Will this register contain 7'b000_0000 (No error event) (from the 2nd xfer) or will it contain information about the error in the first transfer?

When content is persistent, how can I reset it?

When content is not persistent: how can I capture the information about bit errors?

[jamesbone]

Is the content of this register persistent? E.g. assuming two transfers where the first one has a bad CRC and the second one is ok. Will this register contain 7'b000_0000 (No error event) (from the 2nd xfer) or will it contain information about the error in the first transfer?

 ANSWER. Once some bit of this register is asserted, it will remain asserted until the register is read. When the register is read it's cleared.

When content is persistent, how can I reset it?

 ANSWER. Yes, it's persistent and is reset when the register is read.

When content is not persistent: how can I capture the information about bit errors?

 ANSWER. You can capture the information by pooling (reading periodicaly the register) or by interrupt using registers CSI2RX_IRQ_STATUS and CSI2RX_IRQ_MASK.

[jamesbone]

Hello Enrico,

We are reviewing the RM internally so we can provide an accurate response.