iMX6ULL with LAN8720 ethernet phy

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

iMX6ULL with LAN8720 ethernet phy

1,892件の閲覧回数
asurti9
Contributor III

Hello iMX community,

I am trying to boot a custom board based on iMX6ULL EVK but with LAN8720 phy.

I have made following changes in U-Boot following the link https://community.nxp.com/t5/i-MX-Processors/iMX6ULL-Ethernet-LAN8720-U-Boot/td-p/1561549, however the u-boot is getting stuck.

Changes which I made are as below:

diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi
index e23d9f40ed..aaa61d9983 100644
--- a/arch/arm/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi
@@ -172,6 +172,8 @@
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        phy-supply = <&reg_peri_3v3>;
+       phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <5>;
        status = "okay";
 
        mdio {
@@ -179,20 +181,27 @@
                #size-cells = <0>;
 
                ethphy0: ethernet-phy@2 {
-                       compatible = "ethernet-phy-id0022.1560";
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
                        reg = <2>;
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
                        clock-names = "rmii-ref";
-
+                       reset-assert-us = <1000>;
+                       reset-deassert-us = <1000>;
+                       status = "okay";
                };
 
                ethphy1: ethernet-phy@1 {
-                       compatible = "ethernet-phy-id0022.1560";
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
                        reg = <1>;
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
                        clock-names = "rmii-ref";
+                       reset-assert-us = <1000>;
+                       reset-deassert-us = <1000>;
+                       status = "okay";
                };
        };
 };
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
index 598eb7df9b..de1947e052 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -234,16 +234,6 @@ static int setup_fec(void)
 
        return 0;
 }
-
-int board_phy_config(struct phy_device *phydev)
-{
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
-
-       if (phydev->drv->config)
-               phydev->drv->config(phydev);
-
-       return 0;
-}
 #endif
 
 #ifdef CONFIG_VIDEO
diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig
index 349c224289..a9b9cf2625 100644
--- a/configs/mx6ull_14x14_evk_nand_defconfig
+++ b/configs/mx6ull_14x14_evk_nand_defconfig
@@ -68,8 +68,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y

Below are the logs which I am getting on the console when I try to boot with above changes:

U-Boot 2023.04+gf8a2983ec8+p0 (Mar 04 2024 - 07:25:04 +0000)

CPU:   i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 54C
Reset cause: POR
Model: i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM:  512 MiB
Core:  74 devices, 22 uclasses, devicetree: separate
NAND:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from NAND... *** Warning - bad CRC, using default environment

[*]-Video Link 0 (480 x 272)
        [0] lcdif@21c8000, video
In:    serial
Out:   serial
Err:   serial
Net:   Could not get PHY for FEC1: addr 1
Could not get PHY for FEC1: addr 1
Get shared mii bus on etherne▒

When I disable fec0 and fec1 node in the u-boot dtsi, it is booting fine, so seems like there is some misconfiguration which is happening for LAN8720.

Can you please let me know if the above changes are correct and if there are any other changes which I need to make?

Also, if you can let me know the related Kernel changes then it would be of great help.

Thanks!
Aliasgar

 

ラベル(2)
タグ(1)
0 件の賞賛
返信
8 返答(返信)

1,844件の閲覧回数
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

From the log info looks like struck at below function: 

struct phy_device *phy_connect(struct mii_dev *bus, int addr,

                   struct udevice *dev,

                   phy_interface_t interface)

{

    struct phy_device *phydev = NULL;

    uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;

   ......

}

The add has problem causing mask could not be correct parse.

phydev = phy_find_by_mask(bus, mask);

Could you add more print info with below function?

get_phy_device_by_mask

And we also suggest to make below device tree definition:

&fec1 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_enet1>;

    phy-mode = "rmii";

    phy-handle = <&ethphy0>;

    phy-supply = <&reg_peri_3v3>;

    status = "okay";

};

Wish it helps.

best regards,

Mike

0 件の賞賛
返信

1,814件の閲覧回数
asurti9
Contributor III

Hello @Hui_Ma ;

Thanks for the response!

I tried adding more print messages and realised that below function is called 3 times:

struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface)

and so below function:

struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)

When the above function is called 3rd time, the u-boot is getting stuck at below location:

/*
* Grab the bits from PHYIR1, and put them
* in the upper half
*/
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);

under get_phy_id.

In dts, we have fec0 and fec1. But don't know why it is trying to call phy_connect 3rd time. I believe as the device is not present in the tree, phy driver is crashed.

I have tried the dts as you mentioned. But it is not working.

Also, I believe SMSC driver should be getting probed as we are using LAN8720 phy. But not sure if it is happening.

Can you please provide any leads where else I can look into?

Thanks!
- Ali

0 件の賞賛
返信

1,739件の閲覧回数
Hui_Ma
NXP TechSupport
NXP TechSupport

Hello Ali,

Please refer below suggestions:

1. Please keep the compatible field change of dts file, remove other modifications temporaryly. 

    If you want to add below gpio control, please add related pinctrl node accordingly.  

phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;

2. Please add print info in SMSC driver.

3. Please notice the file location: using board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c instead of board/freescale/mx6ullevk/mx6ullevk.c

Hui_Ma_1-1717052263103.png

 

Wish it helps.

Mike

 

0 件の賞賛
返信

1,728件の閲覧回数
asurti9
Contributor III

Hello @Hui_Ma ,

Thanks for the response.

Below are the changes which I have made as per your suggestion:

DTSI changes:

diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi
index e23d9f40ed..20ee8065e7 100644
--- a/arch/arm/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi
@@ -163,6 +163,8 @@
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
        phy-supply = <&reg_peri_3v3>;
+       phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <5>;
        status = "okay";
 };
 
@@ -172,24 +174,26 @@
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        phy-supply = <&reg_peri_3v3>;
+       phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <5>;
        status = "okay";
-
        mdio {
                #address-cells = <1>;
                #size-cells = <0>;
-
                ethphy0: ethernet-phy@2 {
-                       compatible = "ethernet-phy-id0022.1560";
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
                        reg = <2>;
+
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
                        clock-names = "rmii-ref";
-
                };
-
                ethphy1: ethernet-phy@1 {
-                       compatible = "ethernet-phy-id0022.1560";
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       smsc,disable-energy-detect;
                        reg = <1>;
+
                        micrel,led-mode = <1>;
                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
                        clock-names = "rmii-ref";

mx6ul_14x14_evk board file change:

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index b033cb01e6..996de4a39f 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -314,15 +314,6 @@ static int setup_fec(void)
        return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-       phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
-
-       if (phydev->drv->config)
-               phydev->drv->config(phydev);
-
-       return 0;
-}
 #endif
 
 #ifdef CONFIG_VIDEO

defconfig change:

diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig
index 349c224289..a9b9cf2625 100644
--- a/configs/mx6ull_14x14_evk_nand_defconfig
+++ b/configs/mx6ull_14x14_evk_nand_defconfig
@@ -68,8 +68,7 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_PHY_SMSC=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y

print info under smsc driver:

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 7740a2510d..51ec89cbab 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -16,6 +16,7 @@
 static int smsc_parse_status(struct phy_device *phydev)
 {
        int mii_reg;
+       printf("************ inside smsc_parse_status *********\n");
 
        mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
 
@@ -35,6 +36,7 @@ static int smsc_parse_status(struct phy_device *phydev)
 static int smsc_startup(struct phy_device *phydev)
 {
        int ret;
+       printf("************ inside smsc_startup *********\n");
 
        ret = genphy_update_link(phydev);
        if (ret)
@@ -105,6 +107,7 @@ static struct phy_driver lan8742_driver = {
 
 int phy_smsc_init(void)
 {
+       printf("******* inside phy_smsc_init ********\n");
        phy_register(&lan8710_driver);
        phy_register(&lan911x_driver);
        phy_register(&lan8700_driver);

After making above changes, I am getting print log from the smsc driver, but again it is getting stuck. Please find below logs:

U-Boot 2023.04+gf8a2983ec8+p0 (Mar 04 2024 - 07:25:04 +0000)

CPU:   i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 49C
Reset cause: POR
Model: i.MX6 ULL 14x14 EVK Board
Board: MX6ULL 14x14 EVK
DRAM:  512 MiB
Core:  74 devices, 22 uclasses, devicetree: separate
NAND:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from NAND... *** Warning - bad CRC, using default environment

[*]-Video Link 0 (480 x 272)
        [0] lcdif@21c8000, video
In:    serial
Out:   serial
Err:   serial
Net:   ******* inside phy_smsc_init ********
Could not get PHY for FEC1: addr 1
Could not get PHY for FEC1: addr 1
Get shared mii bus on etherne

It has just printed smsc_init log. So it is trying to register the smsc phy it seems. So any pointers where I can find the actual error?

Thanks,
Ali

0 件の賞賛
返信

1,685件の閲覧回数
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

Sorry for the later reply.

Could you help to provide the ENET PHY related circuit? Thanks.

Best regards,

Mike

0 件の賞賛
返信

1,682件の閲覧回数
asurti9
Contributor III

Hello @Hui_Ma ,

Attached the ENET PHY circuit connection.

Thanks,

Ali

0 件の賞賛
返信

1,639件の閲覧回数
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi,

Sorry for the later reply.

The Ethernet PHY related circuit should be correct.

Could you measure the [ENET1_RESET]/[ENET2_RESET] voltage? If the PHY RESET pad voltage is high?

And please check if there has 50MHz input reference clock at PHY [CLKIN] pad?

Thank you.

Mike 

0 件の賞賛
返信

1,757件の閲覧回数
Hui_Ma
NXP TechSupport
NXP TechSupport

Hi Ali,

I am checking with this issue and will let you know later.

Thank you for the patience.

Best regards,

Mike

0 件の賞賛
返信