iMX6 IPU IPU_SRM_PRI2 Register

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iMX6 IPU IPU_SRM_PRI2 Register

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Contributor III

In the iMX6DQ SDK ipu_dp.c file, in the ipu_dp_csc_config function there is the following line:

ipu_write_field(ipu_index, IPU_IPU_SRM_PRI2__DP_S_SRM_MODE, 3);

When I read the DP_S_SRM_MODE field back after writing a 3 to it, it reads back as 2. I'm assuming this field is self-clearing to 2 (which the RM says is reserved) after the update now operation is finished. Is this correct?

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NXP TechSupport
NXP TechSupport

SRM_MODE can be 00, 10 or 11. If the SW set to 11: after the update the state machine is automatically moved to 10 mode.

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NXP TechSupport
NXP TechSupport

SRM_MODE can be 00, 10 or 11. If the SW set to 11: after the update the state machine is automatically moved to 10 mode.

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