imx6 solo uSDHC clock gating register, which description is correct

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

imx6 solo uSDHC clock gating register, which description is correct

859件の閲覧回数
hailiu
Contributor IV

I am trying to enable uSDHC module clock of iMX6 solo, when Iread through the reference manual (IMX6SDLRM.pdf), I am a little bit confused. in page 791, table 18-3, it says the clocks for module 1\2\3\4 are enabled by CCGR5(CG1,CG2,CG3,CG4) rspectively. In page 804, Fig18-7, it shows that the clocks are controlled by CCGR6(CG0:CG1:CG2:CG3) respectively. Inpage 878-879, it shows that these clocks are controlled by CCGR6(CG1:CG2:CG3:CG4) respectively, CG0 is used to control USB clock. I guess the correct one should be CCGR6(CG1-CG4), Am I right?

0 件の賞賛
返信
1 返信

843件の閲覧回数
Rita_Wang
NXP TechSupport
NXP TechSupport

uSDHC.PNG

Yes, your mind is right.