I just want to clarify what the final routed length of this trace needs to be. AN4215 specifies that the total routed length needs to be
CLK routed distance + DQS routed distance.
I have 2 byte lanes in my DDR2 interface so I have DQS0 and DQS1.
I want to confirm what the correct interpretation is. Is it...
total routed length = CLK + DQS0 + DQS1
or
total routed length = CLK + (DQS0 or DQS1)
I believe that the latter is correct....
Thanks in advance.
已解决! 转到解答。
HI Nicholas
best value would be the middle value between the two lengths
mean ( EMI_CLK+EMI_CLKn , DQS0+DQS0n, DQS1+DQS1n )
Best regards
igor
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HI Nicholas
best value would be the middle value between the two lengths
mean ( EMI_CLK+EMI_CLKn , DQS0+DQS0n, DQS1+DQS1n )
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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