iMX283 EMI_DDR_OPEN routed Length

[nipri]

I just want to clarify what the final routed length of this trace needs to be. AN4215 specifies that the total routed length needs to be

CLK routed distance + DQS routed distance.

I have 2 byte lanes in my DDR2 interface so I have DQS0 and DQS1.

I want to confirm what the correct interpretation is. Is it...

total routed length = CLK + DQS0 + DQS1

or

total routed length = CLK + (DQS0 or DQS1)

I believe that the latter is correct....

Thanks in advance.

[igorpadykov · Accepted solution]

HI Nicholas

best value would be the middle value between the two lengths

mean ( EMI_CLK+EMI_CLKn , DQS0+DQS0n, DQS1+DQS1n )

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[nipri]

Thanks! Your solution is close to my 2nd interpretation though more accurate than using one or the other (keeping in mind that my CLK and DQS traces are all equal in length to within 50 mils.)