iMX28 GPIO interrupt capacibilty

[x10]

Hi, all

As I understand that all the GPIO pins of iMX28 can be set as interrupt input pins triggered with either level or edge. But I can not find the info about interrupt input signal which can trigger iMX28 through its' gpio pins. For example, what is the minimum pulse width in falling edge trigger mode. Please let me know if anybody have related information about imx28 gpio interrupt. Thanks in advance.

BR

Cheng Shi

emtronix

[wolfgang_gaerbe]

Hi Chen,

So you have slightly more than 8us (during startbit of 115k uart transmission) to start your receiving spi fifo.

Nice idea.

rgds.

[x10]

Thanks Wolfgang. 

Actually, more UART ports are added, which based on spi. UART's interrupt connect to iMX28's GPIO which can be triggered with 84ns width interrupt pulse. That's the exactly situation I met. Anyway, the interrupt is work!

BR

Cheng Shi 

[wolfgang_gaerbe]

Hi Cheng,

If it boils down to GPIO documentation, the available information is as verbose and precise as the rest of that spec.

The official answer from fsl is "that software is always way slower than hardware - so don´t bother".

Here a small summary of my benchmark tests - assuming that your ABPX clock is 24MHz.

1.) Write any register (includes setting a GPIO PIN) on the ABPX bus with the processor takes 1-2 ABPX clock cycles,

depending on the actual phase relation of Processor clock and ABPX clock.

So writing will give a latency of 42 to 84ns.

The first write is non-blocking - if you perform consecutive writes to the ABPX bus there will be a runtime penality with the same timing.

2.) Read any register to the ABPX BUS (includes reading a gpio pin) with the processor takes 2-4 ABPX clock cycles due to the fact that there are 2 accesses needed in terms of the AHB to ABPX bridge.

So reading will give a latency of 84 to 168ns - with a mandatory minimum runtime penality of 84 ns.

3) There is no ABPX bridge involved in IRQ signaling - just the needed time to readout the status (which needs again an ABPX read operation) - so the latency might be similar as other irq.

4) Because of the fact that the GPIO Block (IP Block) is operated with ABPX clock - i assume that the minimum pulse duration is 2 ABPX clock cycles minimum including some safe margin.

So the answer to your question would be _84ns_ minimum. (24MHz ABPX operation).