Can someone point me to documentation on how configure, enable, and test DRAM ECC on the i.mx 8QuadMax? IMX8QMRM indicates ECC on DRAM is supported but I can't find any details on how to enable it.
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Correct this answer, i.MX8QM doesn't support ECC, iMX8DXL support this, the ECC keyword in reference manual and DDR script doesn't mean it supports ECC.
> IMX8QMRM indicates ECC on DRAM
I think I have to take that back, the manual mentions ECC in the DDR Controller section but no where do I find it saying it is supported. Given that and the lack of documentation on how to configure it I am guessing ECC on DRAM is not supported.
The default setting has enabled the ecc feature, can you share if you are facing issue in your product.
Are you saying the i.mx8qm supports ecc on DRAM and turns it on by default at processor startup?
If so:
1) Can you point me to where this is documented?
2) What is the processor response when a non-correctable double bit DRAM ecc error occurs?
3) If there a way to inject ecc errors in DRAM so fault response can be tested?
Correct this answer, i.MX8QM doesn't support ECC, iMX8DXL support this, the ECC keyword in reference manual and DDR script doesn't mean it supports ECC.