Hi
I need to connect the iMX8QM to a PCIe peripheral using a dual lane setup. As I did not found any hints for the dual lane use case, maybe someone can confirm my setup:
i.MX8QM | PCIe Peripheral | Note |
PCIE0_RX0_N | PCIE_TX0_N | via 220nF capacitor in series, close to peripheral |
PCIE0_RX0_P | PCIE_TX0_P | via 220nF capacitor in series, close to peripheral |
PCIE0_TX0_N | PCIE_RX0_N | via 220nF capacitor in series, close to IMX8 |
PCIE0_TX0_P | PCIE_RX0_P | via 220nF capacitor in series, close to IMX8 |
PCIE1_RX0_N | PCIE_TX1_N | via 220nF capacitor in series, close to peripheral |
PCIE1_RX0_P | PCIE_TX1_P | via 220nF capacitor in series, close to peripheral |
PCIE1_TX0_N | PCIE_RX1_N | via 220nF capacitor in series, close to IMX8 |
PCIE1_TX0_P | PCIE_RX1_P | via 220nF capacitor in series, close to IMX8 |
PCIE_CTRL0_CLKREQ_B | CLKREQ_B | 1kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3 |
PCIE_CTRL0_PERST_B | PERST_B | 1.8kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3 |
PCIE_CTRL0_WAKE_B | WAKE_B | 1kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3 |
VDD_PCIE_DIG_1P8_3P3 | connected to 1.8V supply | peripheral needs 1.8V level on CLKREQ_B, PERST_B and WAKE_B pins |
PCIE_CTRL1_CLKREQ_B | not used for PCIe | used as 1.8V GPIO |
PCIE_CTRL1_PERST_B | not used for PCIe | used as 1.8V GPIO |
PCIE_CTRL1_WAKE_B | not used for PCIe | used as 1.8V GPIO |
PCIE_SATA_REFCLK100M_N | PCIE_REFCLK_N | iMX8QM configured as 100MHz clock output |
PCIE_SATA_REFCLK100M_P | PCIE_REFCLK_P | iMX8QM configured as 100MHz clock output |
PCIE0_PHY_PLL_REF_RETURN | connected via 220nF series capacitor to VDD_PCIE_LDO_1P8 | |
PCIE1_PHY_PLL_REF_RETURN | connected via 220nF series capacitor to VDD_PCIE_LDO_1P8 | |
PCIE_SATA0_PHY_PLL_REF_RETURN | connected via 220nF series capacitor to VDD_PCIE_LDO_1P8 | |
PCIE_REXT | connected via 845ohm series resistor to PCIE0_PHY_PLL_REF_RETURN | |
PCIE_REF_QR | connected via 453ohm series resistor to GND |
As the SATA interface is not used:
PCIE_SATA0_RX0_N is not connected
PCIE_SATA0_RX0_P is not connected
PCIE_SATA0_TX0_N is not connected
PCIE_SATA0_TX0_P is not connected
Question 1: are pinout and connections feasible?
Question 2: I read that using PCIE_SATA_REFCLK100M as clock output is possible but not recommended. Is there another reason besides the missing ability of spread spectrum clocking?
Thanks a lot.
Solved! Go to Solution.
Question a: For a dual lane setup do I have to use either
or
--------------------
it is "PCIE_CTRL0_*"
>Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe >peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special >termination to make the dual lane setup work?
yes they can be used as as generic GPIOs.
>Question c: Where can I get more information to understand this internal clock instability. I guess this >information is available under NDA only - but can you give me some hints about what I have to ask my >sales support for (e.g. a document name)?
for PCIe clock stability there is no factory testing performed.
Best regards
igor
Hi Klaus
>Question 1: are pinout and connections feasible?
for hardware connections one can look at i.MX8QM MEK schematic MCIMX8QM-CPU MEK – Schematics
and recommendations provided in i.MX 8QuadMax/i.MX 8QuadXPlus Hardware Developer’s Guide
dts example:
>Question 2: I read that using PCIE_SATA_REFCLK100M as clock output is possible but not
>recommended. Is there another reason besides the missing ability of spread spectrum clocking?
internal clock may have instability which may affect PCIe compliance testing.
Best regards
igor
Hallo Igor
Thanks for the fast reply.
As far as I understand it, iMX8QM MEK only implements two single lane PCIe interfaces.
I explicitly need help to implement the dual lane setup, so the MEK is there no help. Also the Hardware Design Guide does not give any information for a dual lane setup.
So lets brake it down to following questions:
Question a: For a dual lane setup do I have to use either
or
Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special termination to make the dual lane setup work?
Question c: Where can I get more information to understand this internal clock instability. I guess this information is available under NDA only - but can you give me some hints about what I have to ask my sales support for (e.g. a document name)?
Kind regards.
Klaus
Question a: For a dual lane setup do I have to use either
or
--------------------
it is "PCIE_CTRL0_*"
>Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe >peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special >termination to make the dual lane setup work?
yes they can be used as as generic GPIOs.
>Question c: Where can I get more information to understand this internal clock instability. I guess this >information is available under NDA only - but can you give me some hints about what I have to ask my >sales support for (e.g. a document name)?
for PCIe clock stability there is no factory testing performed.
Best regards
igor