i.MX8QM PCIe dual lane pinout and connections

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i.MX8QM PCIe dual lane pinout and connections

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K_Steinhammer
Contributor III

Hi

I need to connect the iMX8QM to a PCIe peripheral using a dual lane setup. As I did not found any hints for the dual lane use case, maybe someone can confirm my setup:

i.MX8QMPCIe PeripheralNote
PCIE0_RX0_NPCIE_TX0_Nvia 220nF capacitor in series, close to peripheral
PCIE0_RX0_PPCIE_TX0_Pvia 220nF capacitor in series, close to peripheral
PCIE0_TX0_NPCIE_RX0_Nvia 220nF capacitor in series, close to IMX8
PCIE0_TX0_PPCIE_RX0_Pvia 220nF capacitor in series, close to IMX8
PCIE1_RX0_NPCIE_TX1_Nvia 220nF capacitor in series, close to peripheral
PCIE1_RX0_PPCIE_TX1_Pvia 220nF capacitor in series, close to peripheral
PCIE1_TX0_NPCIE_RX1_Nvia 220nF capacitor in series, close to IMX8
PCIE1_TX0_PPCIE_RX1_Pvia 220nF capacitor in series, close to IMX8
PCIE_CTRL0_CLKREQ_BCLKREQ_B1kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3
PCIE_CTRL0_PERST_BPERST_B1.8kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3
PCIE_CTRL0_WAKE_BWAKE_B1kohm pull up resistor to VDD_PCIE_DIG_1P8_3P3
   
VDD_PCIE_DIG_1P8_3P3connected to 1.8V supplyperipheral needs 1.8V level on CLKREQ_B, PERST_B and WAKE_B pins
   
PCIE_CTRL1_CLKREQ_Bnot used for PCIeused as 1.8V GPIO
PCIE_CTRL1_PERST_Bnot used for PCIeused as 1.8V GPIO
PCIE_CTRL1_WAKE_Bnot used for PCIeused as 1.8V GPIO
   
PCIE_SATA_REFCLK100M_NPCIE_REFCLK_NiMX8QM configured as 100MHz clock output
PCIE_SATA_REFCLK100M_PPCIE_REFCLK_PiMX8QM configured as 100MHz clock output
   
PCIE0_PHY_PLL_REF_RETURN connected via 220nF series capacitor to VDD_PCIE_LDO_1P8
PCIE1_PHY_PLL_REF_RETURN connected via 220nF series capacitor to VDD_PCIE_LDO_1P8
PCIE_SATA0_PHY_PLL_REF_RETURN connected via 220nF series capacitor to VDD_PCIE_LDO_1P8
PCIE_REXT connected via 845ohm series resistor to PCIE0_PHY_PLL_REF_RETURN
PCIE_REF_QR connected via 453ohm series resistor to GND

 

As the SATA interface is not used:

PCIE_SATA0_RX0_N is not connected
PCIE_SATA0_RX0_P is not connected
PCIE_SATA0_TX0_N is not connected
PCIE_SATA0_TX0_P is not connected

 

Question 1: are pinout and connections feasible?

Question 2: I read that using PCIE_SATA_REFCLK100M as clock output is possible but not recommended. Is there another reason besides the missing ability of spread spectrum clocking?

Thanks a lot.

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igorpadykov
NXP TechSupport
NXP TechSupport

Question a: For a dual lane setup do I have to use either

  • PCIE_CTRL0_CLKREQ_B
  • PCIE_CTRL0_PERST_B
  • PCIE_CTRL0_WAKE_B

or

  • PCIE_CTRL1_CLKREQ_B
  • PCIE_CTRL1_PERST_B
  • PCIE_CTRL1_WAKE_B

--------------------

 

it is "PCIE_CTRL0_*"

 

>Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe >peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special >termination to make the dual lane setup work?

 

yes they can be used as as generic GPIOs.

 

>Question c: Where can I get more information to understand this internal clock instability. I guess this >information is available under NDA only - but can you give me some hints about what I have to ask my >sales support for (e.g. a document name)?

 

for PCIe clock stability there is no factory testing performed.

 

Best regards
igor

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Klaus

 

>Question 1: are pinout and connections feasible?

 

for hardware connections one can look at i.MX8QM MEK schematic MCIMX8QM-CPU MEK – Schematics

and recommendations provided in   i.MX 8QuadMax/i.MX 8QuadXPlus Hardware Developer’s Guide

dts example:

https://github.com/boundarydevices/linux-imx6/blob/boundary-imx_5.4.x_2.3.0/arch/arm64/boot/dts/free...

 

>Question 2: I read that using PCIE_SATA_REFCLK100M as clock output is possible but not
>recommended. Is there another reason besides the missing ability of spread spectrum clocking?

 

internal clock may have instability which may affect PCIe compliance testing.

 

Best regards
igor

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K_Steinhammer
Contributor III

Hallo Igor

Thanks for the fast reply.

As far as I understand it, iMX8QM MEK only implements two single lane PCIe interfaces.

I explicitly need help to implement the dual lane setup, so the MEK is there no help. Also the Hardware Design Guide does not give any information for a dual lane setup.

So lets brake it down to following questions:

Question a: For a dual lane setup do I have to use either

  • PCIE_CTRL0_CLKREQ_B
  • PCIE_CTRL0_PERST_B
  • PCIE_CTRL0_WAKE_B

or

  • PCIE_CTRL1_CLKREQ_B
  • PCIE_CTRL1_PERST_B
  • PCIE_CTRL1_WAKE_B

Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special termination to make the dual lane setup work?

Question c: Where can I get more information to understand this internal clock instability. I guess this information is available under NDA only - but can you give me some hints about what I have to ask my sales support for (e.g. a document name)?

Kind regards.

  Klaus

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668 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Question a: For a dual lane setup do I have to use either

  • PCIE_CTRL0_CLKREQ_B
  • PCIE_CTRL0_PERST_B
  • PCIE_CTRL0_WAKE_B

or

  • PCIE_CTRL1_CLKREQ_B
  • PCIE_CTRL1_PERST_B
  • PCIE_CTRL1_WAKE_B

--------------------

 

it is "PCIE_CTRL0_*"

 

>Question b: Can I use the 3 pins (CLKREQ_B, PERST_B and WAKE_B) not connected to the PCIe >peripheral (see question a) as generic GPIOs for other (non PCIe) functions, or do they need special >termination to make the dual lane setup work?

 

yes they can be used as as generic GPIOs.

 

>Question c: Where can I get more information to understand this internal clock instability. I guess this >information is available under NDA only - but can you give me some hints about what I have to ask my >sales support for (e.g. a document name)?

 

for PCIe clock stability there is no factory testing performed.

 

Best regards
igor