Hello,
i´m working on the test of the i.MX8M and have a question to the processor´s bsdl file:
Before it mentions the "attribute compliance pattern" it says:
"It lists a set of design ports and the values that they should be set to, in order to enable compliance to IEEE Std 1149.1"
How strict is the part "should be set to" meant?
And which pins are absolutely necessary to achieve JTAG mode?
Thanks for your help!
Martin
Hello,
Please use Design checklist table in i.MX 8MDQLQ Hardware Developer’s Guide.
https://www.nxp.com/docs/en/user-guide/IMX8MDQLQHDG.pdf
In particular, look at Recommended JTAG board terminations table.
Also, JTAG_MOD should be pulled up for Boundary Scan.
Pay attention on the following from the BSDL file:
attribute COMPLIANCE_PATTERNS of chip: entity is
"(BOOT_MODE0, BOOT_MODE1, GPIO1_IO00, GPIO1_IO01, GPIO1_IO02, " &
"GPIO1_IO03, TEST_MODE) (0000011)";
That is - to use Boundary Scan, the pin TEST_MODE must be on HIGH level.
Have a great day,
Yuri
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