i.MX6ULL eCSPI1 Slave mode: MISO does not go high impedance

[chris_f]

I'm able to use the eCSPI1 module in slave mode but when attaching other slaves to the same bus I'm getting conflict on the MISO line.

I've tried using two different pins for MISO (LCD_DATA23 and CSI_DATA07) but the result is the same. The pins do not go hi-Z when the SS line is deasserted.

I can't find any mention of this problem in errata.

Can someone confirm that the module works correctly in this respect?

[igorpadykov]

Hi chris_f

i.MX6ULL pads have not high impedance ability, one can use open drain

ODE bit (Open Drain Enable Field) in IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23

register. Below example pad settings in dts file:

        pinctrl_ecspi1_1: ecspi1grp-1 {
            fsl,pins = <
                MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0

linux-imx.git - i.MX Linux Kernel 

Best regards
igor
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[chris_f]

Thanks igor but open drain will not help. The MISO pin stays low so will still conflict with other slaves that need to drive high.

Figure 36 of IMX6ULIEC Rev. 2.2, 05/2017 suggests strongly that MISO will go tri-state but does not specify delays.

On every other SPI chip I've used MISO goes tri-state when SS is inactive. Even an Allwinner IC I'm using goes tri-state properly.

I guess I'll have to include a 74AHC1G125 tri-state buffer to fix the problem.