Hello,
I am using an i.MX6SX which is coupled to an FPGA via the EIM interface. I use all four chip selects, resulting in an address space of 32MB per chip select. After a long search for errors, I have now noticed that the address bit 24 drives the value of bit 25. This means that every time I access CS0 or CS2 bit 24 is low and every time I access CS1 or CS3 bit 24 is high. In my opinion, the 32MB address space should include bit 24 as a valid bit and therefore should be determind thru the address I try to access. Bit 25 and bit 26 are allways low.
Anyone have any ideas what could be causing this behavior? Am I missing something?
Let me know if you need any further information.
Thanks in advance.
Best regards
Robin
