i.MX6Q - Problem with using SPI

[tasukuwatanabe]

Dear NXP community,

I am developing a custom board based on the imx6qsabresd board.

Since I want to boot from NOR flash, I am trying to access flash first.
There is a NOR flash connected to ECSPI 1 on my board.

For the time being, NOR flash seems to be working, but the following things are worrisome.

1. Why does not it work on SoC's native CS?
   
   Currently it only works with GPIO configuration.
   Is there a way to make it work with native CS?
   Or does not it work with native CS?
   Please tell me about both u-boot and linux.
   
   
2. Confused by clock polarity, phase setting
   
   Currently I am confused about SPI clock setting (polarity, phase).
   Linux is operating with cpol = 0, cpha = 1 configuration.
   On the other hand, I did not change the setting on u-boot,
   but when I looked at the value of the register both were 0.
   According to the NOR Flash data sheet, input data is latched at the rising edge of the clock and output data can be used from the falling edge.
   Charts with cpol = 0, cpha = 0 or cpol = 1 cpha = 1 are listed together.
   What's happening?
   

Details of what I did are as follows.

When starting up the device, the following message was displayed.

u-boot

SF: Unsupported flash IDs: manuf 00, jedec 0000, ext_jedec 0000

linux

m25p80 spi0.1: unrecognized JEDEC id bytes: 00,  0,  0

About Linux, The configuration of the device tree at this time is as follows.

&ecspi1 {
       fsl,spi-num-chipselects = <2>;
       pinctrl-names = "default";
       pinctrl-0 = <&pinctrl_ecspi1>;
       cs-gpios = <0>,<0>;
       status = "okay";

       flash: n25q128a13@1 {
             #address-cells = <1>;
             #size-cells = <1>;
             compatible = "micron,n25q128a13", "jedec,spi-nor";
             reg = <1>;
             spi-max-frequency = <108000000>;
       };
 };
 ----------
       pinctrl_ecspi1: spi1grp {
             fsl,pins = <
                   MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
                   MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
                   MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
                   MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x100b0
                   MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
             >;
       };

I changed it while trial and error.

Change the CS pin to GPIO setting and register that GPIO to cs-gpios.

cs-gpios = <0>,<&gpio3 19 0>;
MX6QDL_PAD_EIM_D19__GPIO3_IO19

Then I got the value, but the value is wrong.

m25p80 spi0.1: unrecognized JEDEC id bytes: 10, dd, c

I tried setting clock polarity and phase.
Add the following properties to the flash node.

spi-cpha;

Then I got following messages.

m25p80 spi0.1: n25q128a13 (16384 Kbytes)

Next, I changed to u-boot as follows.

I found the SPI code so I activated that macro.

#define CONFIG_SYS_BOOT_SPINOR

I set IOMUX in the boot process code (mx6sabresd.c) on the board. And since there was a code to use GPIO as CS, I set up GPIO just like I did on Linux.

static iomux_v3_cfg_t const ecspi1_pads[] = {
      MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
      //MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
      MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
};

static void setup_spi(void)
{
      imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}

int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
      return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
}

Then I got following messages.

SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

All suggestions are welcome.

Best regard,
Tasuku.

[igorpadykov]

Hi Tasuku

for linux ecspi please look at imx6q-sabreauto-ecspi.dts

linux-2.6-imx.git - Freescale i.MX Linux Tree 

and build image for imx6qsabreauto configuration using

sect.5.1 Build configurations attached Yocto Guide.

Supported spi "cs" selections are described in linux documentation:

linux/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt

linux-2.6-imx.git - Freescale i.MX Linux Tree 

Also may be useful to look at Chapter 5 Configuring the SPI NOR

attached Porting Guide.

Best regards
igor
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[tasukuwatanabe]

Hi Igor

Thanks for your reply.

I checked the configuration of the device tree and found that the following values are probably not appropriate.

spi-max-frequency = <108000000>;

When this is changed, it works even without doing strange setting (cpha) on the clock.

So I think my question 2 was solved.

About question 1, I saw at the information you provided.

According to "fsl-imx-cspi.txt", the "cs-gpios" property seems to be required.

Also in the sabreauto config, gpio is used for CS.

Does this suggest that using gpio is better than native CS?

If CS must be GPIO, I will request HW personnel to change pin specifications.

Can not use native CS?

Could you tell me more detail?

Best regard,
Tasuku.

[igorpadykov]

Hi Tasuku

>Can not use native CS?

pelase check available options in spi driver sources drivers/spi/spi-imx.c

Best regards
igor