i.MX6Q PL310: Change L2 cache size in SW

[norishinozaki]

Hello Champs,

Can we limit the amount of cache size used in software?

I understand we can't configure the size in PL310 by coprocessor instructions, but I'm looking for a way to do that by software, if possible.

BR,

N.S.

[Yuri]

Hello,

Please refer to i.MX6Q PL310: Change size of L2 cache

Have a great day,
Yuri

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[norishinozaki]

Hello Yuri,

Thanks, but Artur confirmed that:

>The i.MX6Q L2 cache size of 1MByte is hardwired within the chip and cannot be changed.

i.MX6Q PL310: Change size of L2 cache

So I'm asking other ways....

BR,

N.S.

[Yuri]

Hello,

   One of possible solutions is cache line / way locking approach, but

again -  this is configurable on IP level by SOC designer. According

to Table 12-5 (PL310 L2 Cache configuration) of the i.MX6 D/Q RM,

"Lockdown by line" is supported. To get more details about it we should

use ARM CPU specs. Table 12-2 (Cortex-A9 revision) states that ARM
CPU specs of the i.MX6 D/Q is "MP004-BU-50000-r2p10-0rel0".
This document is not provided on ARM web. Nevertheless, You may

try using the following :

ARM Information Center

Regards,

Yuri.