Hi all,
Our customer is facing a issue while use i.MX6DL + Android 6.0.1 Kernel 3.14 for their product.
While the app running, sometimes the LVDS will hand and show up the following logs (more details please see the attachment):
[71484.964912] [galcore]: GPU[0] hang, automatic recovery.
[71484.970228] [galcore]: recovery done
I check the source code, the log is from ../drivers/mxc/gpu-viv/ driver.
I found a community thread has the similar issue, seems update Kernel may solve the issue.
However, customer is not allowed to upgrade bsp or Kernel right now.
Do NXP have gpu-viv driver update or patch for Kernel 3.14 to solve the issue?
Any suggestion?
Best Regards,
Wayne Kuo
Original Attachment has been moved to: log_0104_app_crash_x3.txt.zip
Solved! Go to Solution.
Hi Bio,
Thanks for your suggestion, customer has solved this issue.
We think this issue cause by customer themselves.
We probe the VDD_PU_CAP voltage on customer'sboard.
We saw the VDD_PU_CAP voltage was cyclical High-to-Low, and which on SabreSD board is stable High.
We tried to set the PMU_REG_CORE register but no luck, seems this register was always been overwrite.
After customer's S/W optimization engineer did some modify and release another Kernel version, the PMU_REG_CORE register can be set to a fix value and VDD_PU_CAP voltage is stable, this iuuse is solved.
We think this issue is cause by unstable VDD_PU_CAP voltage.
Best Regards,
Wayne Kuo
Hi wayne,
your issue is due to: galcore: clk_get vg clock failed, disable vg!
There was a problem with the i.MX6 v2.0 that required that GPu2D and VG Core Clock and Axi Clock to be separated, you may had a previous version of the device and it is having the problem
https://git.congatec.com/arm/qmx6_kernel/commit/765af27537bbbdea4e280823e6eeecbd73f2c604
regards
Hi Bio,
Thanks for your suggestion, customer has solved this issue.
We think this issue cause by customer themselves.
We probe the VDD_PU_CAP voltage on customer'sboard.
We saw the VDD_PU_CAP voltage was cyclical High-to-Low, and which on SabreSD board is stable High.
We tried to set the PMU_REG_CORE register but no luck, seems this register was always been overwrite.
After customer's S/W optimization engineer did some modify and release another Kernel version, the PMU_REG_CORE register can be set to a fix value and VDD_PU_CAP voltage is stable, this iuuse is solved.
We think this issue is cause by unstable VDD_PU_CAP voltage.
Best Regards,
Wayne Kuo