i.MX6 SoloX clock sources

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX6 SoloX clock sources

Jump to solution
345 Views
yan2
Contributor II

Hi,

I am currently designing a board with a i.MX6SoloX.
The reference manual describes two observability clocks, CCM_CLKO1 and CCM_CLKO2, in the Clock Controller Module (CCM).
Unfortunately the pads, where these clocks are provided, are already in use.
Then I've found CCM_CLK1 and CCM_CLK2 as dedicated pins, but no further explanation.
Is there a relation between CCM_CLKO1, CCM_CLKO2 and CCM_CLK1, CCM_CLK2?

As another clock source the BCLK of the EIM is discussed in several threads.
The BCLK is intended for the EIM in synchronous mode, but not recommended for e.g. use as a fpga working clock, although it can be configured as continous clock.
What's the trick with this BCLK?

Best Regards,
Michael

0 Kudos
1 Solution
285 Views
igorpadykov
NXP TechSupport
NXP TechSupport

>I agree, there is neither a specification in the data sheet nor in the reference manual.

>But it is conceivable and propable that there is a timing relation between the internal clock with which the >EIM signals are generated and the continous BCLK in asynchronous mode.

 

sorry it is not formally supported, so if you even manage to experiment and obtain that clock,

it is not guaranteed to work properly. You can try it on own risk. There are no solutions/workarounds/

internal documentation for this use case.

 

Best regards
igor

 

View solution in original post

8 Replies
333 Views
igorpadykov
NXP TechSupport
NXP TechSupport

HI Schulte

 

CCM_CLK1 that corresponds to the anaclk1 (described in CCM_ANALOG_MISC1n,
sect.19.7.16 Miscellaneous Register 1 (CCM_ANALOG_MISC1n)

i.MX 6SoloX Applications Processor Reference Manual  )
is a differential signal that can be configured both as input and output through the CCM_CLK1 pad.
CCM_CLK2 is input only.
BCLK can be configured in EIM EIM_WCR register bit CONT_BCLK_SEL, sect.23.9.7 EIM Configuration Register (EIM_WCR).

 

Best regards
igor

0 Kudos
328 Views
yan2
Contributor II

Hi,

Thanks for response.
Where is described that CCM_CLK1 corresponds to anaclk1?
It's not in section "Miscellaneous Register 1" of the reference manual, is it?

In case that the BCLK is configured as continous clock, and the EIM is operating in asynchronous mode is there still a reliable timing relation between BCLK and the other EIM signals like EIM_ADDRxx, EIM_CSx_B etc.?
Or in other words are the timing specifications in sections 4.9.3.2 and 4.9.3.3 still valid although the EIM operates in asynchronous mode?

Best Regards,
Michael

0 Kudos
316 Views
igorpadykov
NXP TechSupport
NXP TechSupport

>Where is described that CCM_CLK1 corresponds to anaclk1?
>It's not in section "Miscellaneous Register 1" of the reference manual, is it?

 

info was provided from internal team

 

>In case that the BCLK is configured as continous clock, and the EIM is operating in asynchronous mode..

 

BCLK is used only in synchronous mode.

 

Best regards
igor

0 Kudos
310 Views
yan2
Contributor II

Hi Igor,

if I understand the reference manual correctly, the BCLK can also be activated in asynchronous mode. Do you agree with that?
Even in asynchronous mode the EIM signals are generated with an internal clock. That's obvious, isn't it?
So I'm considering if there is a timing relation between BCLK and the internal clock in asynchronous mode.
Maybe the internal team has also more information on this.

Best Regards,
Michael

0 Kudos
304 Views
igorpadykov
NXP TechSupport
NXP TechSupport

>..if there is a timing relation between BCLK and the internal clock in asynchronous mode...

 

formally it is not supported in asynchronous mode, in particular there are no bclk

related timing in sect.4.9.3.4 General EIM Timing-Asynchronous Mode,

Table 45. EIM Asynchronous Timing Parameters   i.MX 6SoloX Applications Processors for Consumer Products - Data Sheet

 

Best regards
igor

0 Kudos
289 Views
yan2
Contributor II

Hi Igor,

I agree, there is neither a specification in the data sheet nor in the reference manual.

But it is conceivable and propable that there is a timing relation between the internal clock with which the EIM signals are generated and the continous BCLK in asynchronous mode.

Since the manual does not contain the fact that CCM_CLK1 corresponds to anaclk1, but this information was made available by the internal team, I see a little chance that there is also more information available about the continous BCLK in asynchronous mode. So, is there more information available?

Best Regards,

Michael

0 Kudos
286 Views
igorpadykov
NXP TechSupport
NXP TechSupport

>I agree, there is neither a specification in the data sheet nor in the reference manual.

>But it is conceivable and propable that there is a timing relation between the internal clock with which the >EIM signals are generated and the continous BCLK in asynchronous mode.

 

sorry it is not formally supported, so if you even manage to experiment and obtain that clock,

it is not guaranteed to work properly. You can try it on own risk. There are no solutions/workarounds/

internal documentation for this use case.

 

Best regards
igor

 

269 Views
yan2
Contributor II

Hi Igor,

Without documentation or information it is not possible.

Thanks for discussing this!

Best Regards,

Michael

0 Kudos