Our i.MX535 based design boots from eMMC via boot fuses. The design also uses pin AB3 (EIM_A18) to connect to the eMMC's reset pin, and possesses a 10k pull-up.
Every so often the board fails to boot, and when we probe various nets while in this failed state, we see that the eMMC's reset pin (driven by AB3) is low, which puts the eMMC into reset. On a normal boot, this net is high as expected.
Looking closer at the iMX535 datasheet, it indicates AB3 will become an output controlled by EXTMC out of reset, however it doesn't specify the state. While executing the ROM boot loader with fuses set to boot from eMMC, would the state of this pin always be known, or could it be a random value? Is there any chance AB3 may be low when the iMX comes out of reset, causing our eMMC to stay in reset when being polled by the ROM boot loader?
Thanks - Andrew
Hi Andrew
i.MX53 datasheet Table 112. 19 x 19 mm Signal Assignments, Power Rails, and I/O
does not specify output value, so it may be random
https://www.nxp.com/docs/en/data-sheet/IMX53CEC.pdf
i.MX6Q datasheet specifies similar signal as low.
Best regards
igor
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