Hello Champs,
My customer is experiencing SRAM data failure.
They switch devices attached to EIM physically from reset and after, first boot flash then to the SRAM.
They are asking if there is cases and possibilities which EIM I/O becomes unstable under this use case.
Best regards,
N.Shinozaki
Solved! Go to Solution.
Hello Artur,
Yes, I meant sharing the same CS in different time.
I've heard some examples of these, they applied because of shortage of numbers of CS in external memory interfaces(not EIM).
I understood it's not a good idea as you explained here.
Thank you!
Best regards,
N.Shinozaki
Don't understand exactly what do you mean as "they switch devices attached to EIM physically". Do you mean that they switch all the EIM address/data/control signals physically (e.g. with an external multiplexing devices) from one device (boot Flash) to another (SRAM)? If so, this is not a good way. The regular way to connect multiple devices to a single EIM bus is to connect them in parallel to all address/data/control signals except of the Chip Select (CSx) ones. Using different chip select signals allows to separate the accesses to different EIM devices. So, for example, a boot Flash can be connected to the CS0 signal, whereas SDRAM - to CS1.
Have a great day,
Artur
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Hello Artur,
Yes, I meant sharing the same CS in different time.
I've heard some examples of these, they applied because of shortage of numbers of CS in external memory interfaces(not EIM).
I understood it's not a good idea as you explained here.
Thank you!
Best regards,
N.Shinozaki