Hello,
I'm looking at the DDR inline ECC functionality of the i.MX 8M Plus SOC, however I was not able to find complete documentation in the reference manual.
The U-Boot code uses the following registers
```
#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
#define DDRC_SBRSTART0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf38)
#define DDRC_SBRRANGE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf40)
```
and they are used in the `ddrc_inline_ecc_scrub()` function.
The reference manual, with reference to the ECC testing functionality, in the register `ECCCFG1` mention `ECCPOISONADDR0/1`, but they are not defined anywhere.
Where can I find documentation for all those registers?
Where can I find additional documentation on the topic?
A similar question was asked months ago, https://community.nxp.com/t5/i-MX-Processors/inline-ECC-in-i-MX8M-Plus/m-p/1212335/highlight/true#M1... but it did not get an answer.
Thanks,
Francesco
