i.MX 8M Nano UltraLite Quad failing LPDDR4 Calibration

[evancornell]

Hello, I've got a custom board using i.MX 8M Nano UltraLite Quad (MIMX8MN5DVPIZAA) and 16Gbit LPDDR4 (Micron MT53E1G16D1FW-046 WT:A).

I previously had a working custom board using i.MX 8M Nano QuadLite (MIMX8MN5DVTJZAA) and 8Gbit LPDDR4 (Micron MT53D512M16D1DS-046 AAT:D) that I used as a starting point for the design. 

Using mscale_ddr_tool_v3.31 and MX8M_Nano_LPDDR4_RPA_v9_068-0051-00.xlsx (attached), I am able to download to iMX8 fine, but then calibration fails. Please see log below with detailed debug output enabled. 

I can provide schematic and layout via email, but I am sure I adjusted all the pin delays in layout for i.MX 8M Nano UltraLite Quad and routing constraints per the HDG. 

Please advise if there's anything else I can check in RPA tool to pass calibration.

Thanks,
Evan

Download is complete
Waiting for the target board boot...

===================hardware_init=====================

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 11:14:49
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1500MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M-nano: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x1000 ****
PMU10: Setting boot clock divider to 32
PMU10: PHY TOTALS - NUM_DBYTES 2 NUM_NIBBLES 4 NUM_ANIBS 10
PMU10: CSA=0x01, CSB=0x00, TSTAGES=0x131F, HDTOUT=5, MMISC=0 DRAMFreq=3200MT DramType=LPDDR4
PMU10: Pstate0 MRS MR01_A0=0xD4 MR02_A0=0x2D MR03_A0=0x31 MR11_A0=0x66
PMU10: Pstate0 MRS MR12_A0=0x4D MR13_A0=0x00 MR14_A0=0x4D MR22_A0=0x16
PMU5: CA bitmap dump for cs 0
PMU5: CAA0 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA1 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA2 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA3 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA4 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU5: CAA5 ffffffffffffffffffffffffffffffffffffffffffffffff
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED