i.MX 6 DDR Stress Test Tool items

[One_Willow]

Hello.

I'm currently running a stress test targeting MX6ULL.
Then, I get the following test results as logs, but I don't know what exactly each test is doing.
I would like to know.

t0.1: data is addr test
t0: memcpy11 SSN test
t1: memcpy8 SSN test
t2: byte-wise SSN test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

Best regards

[One_Willow]

Hello Jorge7u7.

Sorry for the late reply.
Thank you for your detailed reply.

Best regards.

[JorgeCas]

Hello, I hope you are doing well.

DDR stress test will run memory test with different test patterns:

SSN stands for simultaneous switching noise.

t0.1 data is addr test: This test basically programs the source buffer’s data words with its address (and immediately read-verifies), then copies (memcpy) the source buffer to a destination buffer and verifies the data transferred correctly. For example, if the source address being written to is “0x80000008”, the data value of that address is “0x80000008”. Once the source buffer is completely written, the data is transferred to the destination where it is verified. A basic test to ascertain that simple read/writes work.

t0 memcpy11 SSN test: This test is similar to the memcpy11 random pattern test (described below) which makes use of the custom written memcpy11 function. However, this test uses data patterns to help root out SSN and does not increment the starting address. This test also breaks up the total DDR density into four “banks”, where each bank contains a different SSN data pattern.

t1 memcpy8 SSN test: This test performs “memcpy” bursts of various stress patterns (walking ones and walking zeros, A’s followed by 5’s, etc) using copy_words_using_eight_registers to help determine or weed out simultaneous switching signal noise.

t2 byte-wise SSN test: The purpose of this test is to root out any SSN within byte lanes. It accomplishes this by writing byte-wise patterns to one location and the inverse of each byte to the subsequent location. Each of the four bytes values are equal to one another and the test increments the byte pattern as follows (with the inverse value in brackets: 0x00000000 [0xFFFFFFFF]; 0x01010101 [0xFEFEFEFE]; 0x02020202 [0xFDFDFDFD]; … 0xFFFFFFFF [0x00000000].

t3 memcpy11 random pattern test: This test utilizes a custom written memory copy function that issues 11-word load and store multiple instructions, to test the bursting behavior of the DDR interface. Each time through the memcpy11 test, the start address is incremented in steps of four bytes to test different burst access types, especially important when caches are enabled to initiate burst wraps for cache line fills. The data pattern used is pseudo-random. This test also breaks up the total DDR density into four “banks”, where each bank contains a different “seed” for each pseudo-random data pattern.

t4 IRAM_to_DDRv2 test: This test is similar to the IRAM_to_DDRv1 test, but instead transfers the data 1000 times per test to ensure that the data never changes to root out random glitches. Also, the test uses different data patterns than the IRAM_to_DDRv1 test to further root out SSN.

t5 IRAM_to_DDRv1 test: The purpose of this test is to root out any SSN and isolates the DDR read and write accesses by using the IRAM as an intermediate data storage location. This test moves a user defined length of data using the copy_words_using_eight_registers function from DDR to IRAM and then from IRAM to a different DDR location, then compares DDR location 1 and location 2. The data pattern used is pseudo-random.

t6 read noise walking ones and zeros test: This test helps to identify if there any signal integrity issues or cross talk between data lines or other control signals by doing four sets of test on both CSD0 and CSD1 (if CSD1 is populated).

Read from DDR walking ones – this test writes a set of 0xFFFFFFFF followed by a walking ones pattern to memory and then reads it back in a two word burst (if there are issues, the read will not return a one).

Read from DDR walking zeros test – this test writes a set of 0x00000000 followed by a walking zeros pattern to memory and then reads it back in a two word burst (if there are issues, the read will not return zero).

Write to DDR walking ones test – this test will use an STM to write a two word burst to memory a set of 0xFFFFFFFF followed by a walking ones pattern and then reads it back non-burst (if there are issues, the read will not return a one).

Write to DDR walking zeros test – this test will use an STM to write a two word burst to memory a set of 0x00000000 followed by a walking zeros pattern to memory and then reads it back non-burst (if there are issues, the read will not return zero).

Best regards.