how to make SAI1 mclk & MQS to work on IMX6UL evk?

[danielhu]

It seems some other people have encountered similar issues in i.MX community, but I just can't find a solution that can help.

I am trying to enable MQS audio on IMX6UL evk board. there are apparently some examples already in the kernel, e.g. device tree imx6ul-14x14-ddr3-arm2-mqs.dts. I copied these stuff, and could play audio on sound card mqs-audio, but no audio heard or PWM signal observed, so mqs is not working.

It looks like the SAI1 is more or less working, because we can see the TX data signal and bit clock on oscilloscope, but couldn't see MCLK output, here are the pin mapping we are using in device tree:

fsl,pins = <
MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b088
MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
>;

I noticed there is a patch in mainstream kernel to enable "fsl,sai-mclk-direction-output" in device tree, but this patch does not work for us. I think the reason is obvious, it was trying to set the bit 19 of IOMUXC GPR1, which is only useful when pad LCD_DATA00 pin is used for MCLK output (I am  using CSI_DATA01)

Regardless, from my point of view, SAI1 MCLK do not need to output to any pin as long as it can be correctly propagated to MQS, but what should I do other than following lines in device tree:

&mqs {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mqs>;
clocks = <&clks IMX6UL_CLK_SAI1>;
clock-names = "mclk";
status = "okay";
};

During test, CCM_CCGR5 is 333fc3ff, so it seems to be right value to enable the clock we need. 

All in all, I have no idea what goes wrong, can anyone help?

BTW, we are using imx_4.1.15_2.0.0_ga

[weidong_sun]

Hello Hu,

    Except for configuring IOMUX in dts, you also need to configure "SAI1_MCLK_DIR" bit to be 1, try it , please!

Have a great day,
TIC   Weidong Sun

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[danielhu]

Dear Sun,

Thanks for answer, If you are talking about SAI1_MCLK_DIR bit in IOMUXC_GPR1 (bit 19), yes, we did set this bit. But it still does not work. Looking at the IM6ULRM, the bit is only necessary when SAI1.MCLK is configured for LCD_DATA00 mode ALT8. I tried LCD_DATA00 and CSI_DATA01 for MCLK pin output, do not see difference.