how to link Dc's event "DC_EVT_NEW_DATA" with a routine.

[senixsenix]

Since dc execute a routine when event comes.

we should link a event with a routine addr,by using:

_ipu_dc_link_event(...);

The driver link the DC_EVT_NEW_DATA with DC's routine at addr 1 or 12.

_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);

_ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);

On the other side, The driver should init the DC's routine by using:

_ipu_dc_write_tmpl(...).

I found  the diver initialize the  DC's routine at addr 0,2-11,

However, nothing found in the addr 1&12.

so, why?

And, When does the DC_EVT_NEW_DATA be triggered? by DI? How?

the IPU part of RM is so unclear!

please  make the IPU clear?

By the way :

the DC will execute the template word like cpu run codes, until DC meet a  template word with the stop bit enabled?

[qiang_li-mpu_se]

The DC events were triggered by DI counter, but they have priority, in currrent BSP setting, when multi DC events happens, only the highest priority one will be processed.

The DC event was set in _ipu_dc_init(),

    _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);

    _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);

    _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);

With the above code, we can know, 3 DC event had been enabled, New Line, End of Line and New Pixel Data.

Then in ipu_init_sync_panel()

   _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);

   _ipu_dc_write_tmpl(ipu, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);

   _ipu_dc_write_tmpl(ipu, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);

   _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

We can see events (1 NEW_DATA 2 NL, 3 EOL are triggered by DI counter 5, the active line data counter.)

Maybe you can reference to this link: https://community.freescale.com/docs/DOC-98109

I have some non OS IPU code in uboot file "ipu.c", it can help to you understand the IPU DC and DI code. I had used many Macro to make the depends on DC and DI clearly.

[senixsenix]

Dear Li Qiang

Firstly,happy Chinese new year!

thanks for your brilliant answers.

As for the DC micro-enginee, I still have some questions:

1. As different signals (DC_EVT_NL, DC_EVT_EOL,DC_EVT_NEW_DATA) , why they sync to the same Di counter 5？

Does A Di counter be programed to specific event?  A line of  EVT_NEW_DATA correspond a NL and EOL.

2 When DC_EVT_NEW_DATA happens , Dc'll write data to DI.

But It seem DC still write data to DI when DC_EVT_NL, DC_EVT_EOL happens, The micro-codes are almost the same with DC_EVT_NEW_DATA,except the gluelogic bits.

what's the difference between these micro-codes?

3 As for the micro-code at addr 3, it hasn't stop bit, does it means,the micro-enginee continue to exe micro-code at addr 4?

the WRG will write 24-bit data to DI, but where does the 24-bit data come from?

[qiang_li-mpu_se]

For sync mode display, the DC only need do one thing, output data to display data lines. The DI counter 5 is the active data event, it was used to output the display data, this counter had skipped the blank data with its "offset value".

For Q1, all DC events need output display data, NL, EOL and NEW_DATA events do the same thing.

For Q2, in fact, the gluelogic data can also be same, it has no use in this case. As I mentioned, these three events just do the same thing, output data to DI.

For Q3, yes, without stop bit, after finished addr 3 code, addr 4 code will run. For WRG, the 24 bits data should be filled in OPERAND field, so for EOL event, after output display data, 0 will be output to data bus as blank data with WRG command.