help for imx53 with lpddr2 configure

[rainustc]

Hi,

     Everyone, when I configure the LPDDR2(Hynix 4Gb LPDDR2-S4B, H9TP17A8JDACNR-KGM) with IMX53(routing all signals the same length), some ESDCTL register parameters really confuse me especially in read process.

     1, How the  ESDCTL_ESDMISC RALAT  field influence the read process, or does it have relationship with tCL filed in ESDCTL_ESDCFG0?

     2, Even slow the frequency to 50MHz, using MRR command still could not get the right device id in ESDCTL_ESDMRR( all the field filled with 1), but I can use oscilloscope  to get the right device ID on the ddr bus. So the receiving timing configure is wrong in IMX53, but how to?

     3.FRC_MSR field in ESDCTL_MUR can or can't use in LPDDR2? For CA_DL_ABS_OFFSET field in ESDCTL_PDCMPR2, I think  FRC_MSR have influence with LPDDR2, but the datasheet says only for ddr2/ddr3, not for lpddr2....confused....

    4. I can use the ESDCTL to right configue all the timing need in LPDDR2, like BL8、RL6/WL3 etc.... and can get the right response by the oscilloscope, so

      I think the write process (including the MRW command )  is right, because of the oscilloscope  can show the timing, but the receive is a big problem.

     I really don't know  the read mechanism in IMX53, the datasheet do not make it clearly especially the parameter above,  so can I get some help from this community?

    best regards

    from rain.

[Yuri · Accepted solution]

As for RALAT :

While internal Rx FIFO data-in are sampled by the DQS, the FIFO data-out have no

real time indication when data are ready in the FIFO. Internal data-out are

therefore delayed by a preset value of DDR device CAS latency plus the RALAT

number of ESDCTL logic cycles. RALAT should be set to a big (enough) value to

support the additional FIFO stage & board latencies. Optimal values for RALAT

are board dependent and should be found experimentally.

[rainustc]

But how about tDQSCK be treated in iMX53?  In RALAT field it says have extra 2 cycles for LPDDR2.