Dear person in charge,
I have one question about MIPI on i.MX 8M Mini.
Is it possible to access to MIPI from both Cortex-A53 and Cortex-M4?
Thank you for your answer.
I would like to understand more and so let me ask again as below.
Is it possible to execute the following steps?
1. prohibit the access to MIPI-CSI from Cortex-A53 side
2. access to MIPI-CSI from Cortex-M4 side
3. and then, Cortex-M4 is getting image data from CMOS camera via MIPI-CSI
(Just in case, Linux is running on Cortex-A53 and RTOS is running on Cortex-M4)
I think, in above steps, exclusive processing has been considered.
What do you think?
I apologize if I did not make me understand.
What I am trying to say is that the resource of the MIPI-CSI is not accessible for the M4 cortex. This peripheral is only exclusive for the cortex A53. The cortex M4 does not share the resource of the MIPI-CSI with the cortex A53.
The i.MX8MM was created that the high-speed interfaces like USB, MIPI, VPU, and HDMI were controlled by the cortex A53. The cortex M4 was only created to be used as a real-time processor. I hope I made me understand.
Thanks for your answer.
According to the block diagram of the product that is inside the reference manual. The MIPI-CSI Pheriheral is not inside of the peripherals that are shared between the cores.
However, the M4 cortex could access to the memory map of the mipi-csi peripheral, you can program the registers with the M4 cortex. But we cannot guarantee if the cortex M4 will give you the necessary bandwidth. Furthermore, just to remark that this is also not supported in our BSP.