Dear Community,
Our customer uses i.MX 6 Quad.
Although it is BOOT setting by SPI-NOR, the following trouble rarely occurs when resetting is repeated.
[step1] Set POR_B from Low to High.
[step2] i.MX 6 Quad accesses the SPI-NOR and transfers the first 4 KB to the internal RAM.
[step3] No access to the next SPI-NOR.
The customer is investigating the above-mentioned trouble, and when reading the values of SRC_SBMR 1 and SRC_SBMR 2 using JTAG, it was the following value.
>SRC_SBMR1 (addr 0x20D_8004h) Value 0x1C002830
BOOT_CFG4[7:0]:
BOOT_CFG4[7]=0b0 Infinite Loop Enable at start of boot ROM. Disabled
BOOT_CFG4[6]=0b0 Disabled EEPROM recovery
BOOT_CFG4[5:4] =0b01 CS select (SPI only) ECSPIx_SS1
BOOT_CFG4[3]= 0b1 SPI Addressing (SPI only) 3-bytes (24-bit)
BOOT_CFG4[2:0]=0b100 Port Select ECSPI-5
BOOT_CFG1[7:0]
BOOT_CFG1[7:4]=0b0011 Boot from Serial ROM
>SRC_SBMR2 (addr 20D_801Ch) Value 0x22000001
bit31-26 = 0b001000 Reserved. This read-only field is reserved and always has the value 0.
bit25-24 BMOD[1:0]= 0b10
bit4 BT_FUSE_SEL=0b0 Bits of SBMR are overridden by GPIO pins.
bit3 DIR_BT_DIS=0b0 Direct boot from external memory is allowed
bit1-0 SEC_CONFIG[1:0]= 0b01 Open (allows any program image, even if authentication fails)
I think that there is probably no problem.
[Question]
The bit [31:26] of SRC_SBMR2 is explained in the Reference Manual as follows.
This read-only field is reserved and always has the value 0.
However, when reading using JTAG, bit [31: 26] of SRC_SBMR2 is 0b001000, not 0.
Please tell me the meaning of "bit [31: 26] of SRC_SBMR2 is 0b001000".
Best Regards,
Yasushi Hasegawa
