Should the WRITE_LEVELING delay register values be set greater than the worst case delay value measured across boards?
The documents and discussions usually defer to using a model of the design to set the WRITE_LEVELING delay, but from our measurements using the DDR Stress Test, there is significant deviation board to board which may not align with a modeled design center. Proposing to set delays in the shape of the average line but offset to where they are beyond the worst case delays
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Hi jschoen
I am afraid it is not true to use worst case delay value measured
across boards. Ideally board should use own WRITE_LEVELING delay register values.
Difference accross boards may be caused by impedance mismatch or board noise.
One can recheck with sect.3.4 DDR routing rules IMX6DQ6SDLHDG
Best regards
igor
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Igor,
I found this related post : https://community.freescale.com/thread/319387
It suggests sampling 5-10 boards and get calibration values. Then balance the write leveling values (normally average them). This is essentially what we've done....obtained calibration values for a sample build of same board design.
Is it recommended to average the write leveling value or use the worst case delay value?
Thanks.
Joel