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Questions on i.MX6 DDR3 calibration (fly-by topology design)

Question asked by Hector Palacios on Feb 12, 2014
Latest reply on Mar 20, 2014 by Hector Palacios

Hello,

 

We have a design with i.MX6Q and 1GB DDR3. We use the same four Micron DDR3 chips than the SabreSD reference board, but we are not using the T topology. We are using 'fly-by' topology.

 

We have run the calibration utility using the SabreSD init script given with it (MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc) and got different results on two identical boards (same layout).

 

I have some questions regarding the calibration process:

 

1) *Write leveling*

The calibration script says:

// write leveling, based on Freescale board layout and T topology

// For target board, may need to run write leveling calibration

// to fine tune these settings

// If target board does not use T topology, then these registers

// should either be cleared or write leveling calibration can be run

setmem /32 0x021b080c = 0x001F001F

setmem /32 0x021b0810 = 0x001F001F

setmem /32 0x021b480c = 0x001F001F

setmem /32 0x021b4810 = 0x001F001F

 

Considering our board's 'fly-by' topology, should we set these to 0x00000000 and then rerun the calibration?

Or should we use the values calculated in the first calibration (which ran with default value 0x001F001F) and then rerun the calibration?

 

The manual also states: "If write-leveling delay is larger than 0x2f, it is suggested to set the WALAT value on MMDCx_MDMISC register to 1 in the initialization script and re-run the DDR_Stress_Tester."

 

To begin with, I don't understand this note. 0x2f is around 1/5 of a cycle. If this register is capable of producing up to half a cycle skew, why does the calibration manual recommended to set WALAT to 1? The datasheet recommends to set WALAT if the delay is around half a

cycle, not around 1/5.

In the results from my first calibration, three bytes are slightly over this 0x2f value.

 

2) *MMDC Duty cycle fine tuning*

The SabreSD calibration script states:

//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented

//setmem /32 0x021b08c0 = 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

//setmem /32 0x021b48c0 = 0x24911492

 

How can I determine if my board needs such a fine tuning?

What can I expect to improve/worsen when playing with these settings?

 

3) *RALAT*

The SabreSD calibration script states:

//NOTE about MDMISC RALAT:

//MDMISC: RALAT kept to the high level of 5 to ensure stable operation at 528MHz.

//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:

//a. better operation at low frequency

//b. Small performence improvment

 

How do I determine if a certain RALAT value improves or worsens the DDR3 behavior?

 

4) *Calibration*

After a first calibration, I must take the results, write them to the calibration script and rerun the calibration, right?

After the second calibration, should I do the same one more time? Twice more, three times? How do I know when to stop?

What if I see different values on different identical boards? How much difference in the calculated values is reasonable?

Should I always use the most conservative values (longest delays) among all the boards I calibrate? Or the average value?

 

Thank you for your help.

Kind regards,

--
Héctor Palacios

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