Problems with I.MX6Q calibration in Uboot

[AndyHo]

Hi,

We have a imx6q custom board with 2xLPDDR2 memories, the boot_mfg is configured as fix 2x32 lpddr2,

MMDC0 CS0, CS1/MMDC1 CS0 CS1 are all used.

I have found the hw auto calibrations (ZQ, Write leveling, read dqs, read delay,write delay) are implemented in new uboot SPL, and follow Imx6 DDR calibration sample code, so I ready to modify it for my project.
First, I think 2x32 mode is different from x64, all the calibrations must be done for MMDC0 and MMDC1 independently,  The code is implement for x32/x64 mode, so I modify and test the uboot code by add same code for MMDC1 , but it can only work for MMDC0, but fail to work for MMDC1.

My problems are:

1. Which calibration is neccesary for LPDDR2 (ZQ, Write leveling, read dqs, read delay,write delay)?
   If you check reference manual, for example, write leveling calibration should be disable in lpddr2 mode, but the related registers can be configured for lp2_2ch_x32? or Read DQS calibration is neccesary for read/write delay calibration, but the related registers are only for DDR3 x32/x64?

2. Can we use same MMDC0 calibration code for MMDC1 in lpddr2 2x32 mode? if yes, I don't know why it always fail during MMDC1 calibration.

3. MMDC1 ZQ calibration not perform:
   As you can see the result, ZQ calibration can be done for MMDC0, but not work for MMDC1. In reference manual, MMDCx_MPZQHWCTRL is only for channel 0, channel1 ZQ calibration is also control by MMDC0 , so don't know how to perform MMDC1 ZQ calibration because there is no way to triger MMDC1 ZQ.

        PHY0 ZQ_HW_PD_RES = 0x00000016

        PHY0 ZQ_HW_PU_RES = 0x00000018

        PHY1 ZQ_HW_PD_RES = 0x00000000

        PHY1 ZQ_HW_PU_RES = 0x00000000

4.MMDC1 Read DQS/Read delay/Write Delay calibration:
As you can see the result, the MMDC1 calibrations are fail.

=============MMDC0 calibration==================

Ending Read DQS Gating calibration. Error mask: 0x0

Starting Read Delay calibration.

Ending Read Delay calibration. Error mask: 0x0

Starting Write Delay calibration.

Ending Write Delay calibration. Error mask: 0x0

MMDC registers updated from calibration

Read DQS gating calibration:

        MPDGCTRL0 PHY0 = 0x464B0650

        MPDGCTRL1 PHY0 = 0x064C062B

Read calibration:

        MPRDDLCTL PHY0 = 0x48404842

Write calibration:

        MPWRDLCTL PHY0 = 0x312D3732

Status registers bounds for read DQS gating:

        MPDGHWST0 PHY0 = 0x04100001

        MPDGHWST1 PHY0 = 0x040b0001

        MPDGHWST2 PHY0 = 0x03eb0001

        MPDGHWST3 PHY0 = 0x040c0001

=============MMDC1 calibration==================

Ending Read DQS Gating calibration. Error mask: 0x1

Starting Read Delay calibration.

Ending Read Delay calibration. Error mask: 0x5

Starting Write Delay calibration.

Ending Write Delay calibration. Error mask: 0x1

5. The ddrstress tester 1.03 for lpddr2 can run perfectly for LPDDR2 calibrations, I think some configs or procedures are needed or missing for MMDC1/2x32 in uboot code. if no one can help to solve the issue, is it possible to get the source code to trace the difference, even it may work by using software calibration method.

Thank you
Andy

[igorpadykov · Accepted solution]

Hi Andy

seems these calibration procedures were implemented in mainline

uboot, as nxp supports only ddr tester for calibrations.

Please post it to uboot mail list

U-Boot Info Page

Unfortunately sources of ddr tester tool are not available for customers.

Best regards

igor

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[AndyHo]

Hi Igor,

Thank you for the suggestion.

The implementation is based on the document released by NXP, http://www.nxp.com/files/32bit/doc/app_note/AN4467.pdf, same as sample code in sec 19, and some special calibration is not JEDEC standard, so I don't think I can get more support becides NXP.
Actually some of our boards random fail during android burning test, we need to recalibration again and again to find another suitable calibraiton parameters for those boards, I doubt the ddr stress tool calibration result is enough for the LPDDR2 2x32 mode, why not the calibration can be done in realtime?

In this application note, some calibration is implemented for x32 (MMDC0) or DDR3 X64 only, so I do the samething for MMDC1 (2x32, I think), the result should be same as MMDC0, but the test result is fail, so I double check the register in refernce manual (2014/06 rev02), and found some questions, let us forget the uboot code, just discuss the refernce manual and application note.

Quesiton 1:
First, in the imx6 ddr calibration application note sample code, the MMDC0 and MMDC1 perform dqs/read/write calibration separately, does it means every calibration should perform twice in LPDDR2 2x32 mode?( MMDC0 and MMDC1 )? the answer is related to the question 3

Question 2:
Becfore ZQ assert calibration, you must assign CALIB_PER_CS (CS0 or CS1) in MMDCx_MDMISC, In our design 4 cs are used, does it means only one cs of MMDC can be calibrated and another is ignore? which cs is targetted for ZQ calibration in ddr stress tester? we found system get more stable if we disable cs1 access of MMDC0 & 1.

Question 3:

In Reference manual 44.12.31 MMDC PHY ZQ HW control register(MMDCx_MPZQHWCTRL), you can see the description:

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: This register is reserved for channel 1. Channel 1 ZQ is also controlled by MMDC0_MPZQHWCTRL.

you can force a MMDC0 ZQ calibration by assert ZQ_HW_FOR, but how to do it for MMDC1 since it's control by MMDC0? What is the Reserved means? In my test result, MMDC1 ZQ_HW_PD_RES/ZQ_HW_PU_RES are 0x00000000, it means MMDC1 is not perform ZQ calibration even I set one of/both MMDCx_MPZQHWCTRL as A1390003.

Question 4:
Write leveling calibration, in page 3883, you can see the description:

NOTE
In LPDDR2 mode Write-leveling calibration should be disabled.

But in 44.12.33 MMDC PHY Write Leveling Configuration and Error Status Register (MMDCx_MPWLGCR)

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: DDR3_x64, LP2_2ch_x16, LP2_2ch_x32

Is the write leveling calibration necessary for LPDDR2?.

Question 5, Read DQS calibration:
Same as Question 2, only cs0 or cs1 is targetted of each MMDC for read dqs calibraiton? which cs is targetted for ZQ calibration in ddr stress tester? should we target the cs1 for the calibraiton?

Question 6, Read DQS calibration:
I found the read/write delay calibration always fail if I bypass read DQS calibration, but the read DQS calibration register is only for DDR3( see below register description)? is it neccesary to perform read DQS calibration before read/write delay calibration? please note that read/write delay calibration is imx only, not standard, I don't know why I can't bypass read DQS calibration like ddr stress tester did.

44.12.46 MMDC PHY Read DQS Gating Control Register 0(MMDCx_MPDGCTRL0)
Supported Mode Of Operations:
For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64
For Channel 1: DDR3_x64

Andy

[igorpadykov]

Hi Andy

please create new threads for new questions.

Best regards

igor

[AndyHo]

Hi Igor,

OK

Here is the link :

I.MX6 LPDDR2 2x32 mode calibrations

Andy