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I.MX6 LPDDR2 2x32 mode calibrations

Question asked by Andy Ho on Apr 13, 2016
Latest reply on May 4, 2016 by Yuri Muhin

Hi ,

 

We have a IMX6 custom board, LPDDR2 in 2x32 mode, MMDC0 CS0/1, MMDC1 CS0/1 are used.

There is a  sample implementation is based on the document released by NXP,

http://www.nxp.com/files/32bit/doc/app_note/AN4467.pdf, in sec 19, and it has been merged into mainline uboot, why not the calibration can be done in realtime?


Actually some of our boards random fail during android burning test, we need to recalibration again and again to find another suitable calibrated parameters for those boards, I doubt the ddr stress tool (1.03 lpddr2) calibration result is not  for all chip selects.

In this application note, some calibrations are implemented for x32 (MMDC0) or DDR3 X64 only, so I do the samething for MMDC1 (2x32, I think), it should be work for MMDC1, but the test result is fail, so I double check the registers in refernce manual (2014/06 rev02), and found some questions in refernce manual and application note.

 

Question 1: ZQ calibration

In the imx6 ddr calibration application note page 13, you can see the description in list:

For DDR3:

MMDC0_MPZQHWCTRL          

For LPDDR2 2-Channel

MMDC0_MPZQHWCTRL

MMDC1_MPZQHWCTRL

-----------------------------------------------------------------

ZQ_PARA_EN

-----------------------------------------------------------------

Device ZQ calibration parallel enable.

0- Device ZQ calibration is done in serial (CSD0 first and then CSD1).

1- ZQ calibration of both CS is done in parallel, In functional mode, parallel calibration should be preferred for its speed. Choose serial as a for debugging, if ZQ calibration issues are suspected

but I can't found ZQ_PARA_EN field in reference manual, where is it? and it cause question 4.

 

Quesiton 2:ZQ calibration

In the imx6 ddr calibration application note sample code, the MMDC0 and MMDC1 perform dqs/read/write calibration separately, does it means every calibration should perform 4 times in LPDDR2 2x32 mode?( MMDC0 and MMDC1,each CS0 and CS1)? the question is related to the question 3,4

 

Question 3: all calibration,

Before assert ZQ calibration, you must assign CALIB_PER_CS (CS0 or CS1) in MMDCx_MDMISC, In our design 4 cs are used, does it means only one cs of MMDC can be calibrated and another is ignore? which cs is targetted for ZQ calibration in ddr stress tester? we found system get more stable if we disable cs1 access of MMDC0 & 1(ex: 2GB->1GB). so I doubt ddr stress tester only calibration one of cs of each channel

 

Question 4:

ZQ calibration, In Reference manual 44.12.31 MMDC PHY ZQ HW control register(MMDCx_MPZQHWCTRL), you can see the description:

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: This register is reserved for channel 1. Channel 1 ZQ is also controlled by MMDC0_MPZQHWCTRL.

you can force a MMDC0 ZQ calibration by assert ZQ_HW_FOR, but how to do it for MMDC1 since it's control by MMDC0? What does the Reserved means? In my test result, MMDC1 ZQ_HW_PD_RES/ZQ_HW_PU_RES are 0x00000000, it means MMDC1 is not perform ZQ calibration even I set one of/both MMDCx_MPZQHWCTRL to 0xA1390003.

 

Question 5:Write leveling calibration

In ddr calibration application note:

3.2 LPDDR2

All the above calibration processes except DQS gating calibration and write leveling calibration can be

used for LPDDR2 calibration.

 

In reference manual page 3883, you can see the description:

NOTE
In LPDDR2 mode Write-leveling calibration should be disabled.

But in 44.12.33 MMDC PHY Write Leveling Configuration and Error Status Register (MMDCx_MPWLGCR)

Supported Mode Of Operations:
For Channel 0: All
For Channel 1: DDR3_x64, LP2_2ch_x16, LP2_2ch_x32

Is the write leveling calibration necessary for LPDDR2?.

 

Question 6, Read DQS calibration:
Same as Question 2, only cs0 or cs1 is targetted of each MMDC for read dqs calibraiton? which cs is targetted for ZQ calibration in ddr stress tester? should we target the cs1 for the calibraiton? I am afraid only cs0 or cs1 is calibrated in my case.

 

Question 7, Read DQS calibration:

In ddr calibration application note:

3.2 LPDDR2

All the above calibration processes except DQS gating calibration and write leveling calibration can be

used for LPDDR2 calibration.


I found the read/write delay calibration always fail if I bypass read DQS calibration, but the read DQS calibration register is only for DDR3( see below register description)? is it neccesary to perform read DQS calibration before read/write delay calibration? please note that read/write delay calibration is imx only, not standard, I don't know why I can't bypass read DQS calibration like ddr stress tester did.

44.12.46 MMDC PHY Read DQS Gating Control Register 0(MMDCx_MPDGCTRL0)
Supported Mode Of Operations:
For Channel 0: DDR3_x16, DDR3_x32, DDR3_x64
For Channel 1: DDR3_x64

 

Andy

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