Hi, i'm using imx6qsabreauto board, and I have a similar issue with these:
https://community.freescale.com/thread/320124
https://community.freescale.com/message/398545#398545
It works fine when I use kernel 3.0.35-2666-gbdde708.
The logs with kernel 3.10.17-1.0.0_ga+g232293e:
root@imx6qsabreauto:~# uname -a
Linux imx6qsabreauto 3.10.17-1.0.0_ga+g232293e #2 SMP PREEMPT Thu Oct 30 17:15:01 CST 2014 armv7l GNU/Linux
root@imx6qsabreauto:~# dmesg | grep -E 'pci|PCI'
imx6q-pcie 1ffc000.pcie: phy link never came up
imx6q-pcie 1ffc000.pcie: DEBUG_R0: 0x004abc43, DEBUG_R1: 0x08100000
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x1000-0x10000]
pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci_bus 0000:00: scanning bus
pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400
pci 0000:00:00.0: reg 10: [mem 0x00000000-0x000fffff]
pci 0000:00:00.0: reg 38: [mem 0x00000000-0x0000ffff pref]
pci 0000:00:00.0: calling pci_fixup_ide_bases+0x0/0x3c
pci 0000:00:00.0: supports D1
pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
pci 0000:00:00.0: PME# disabled
pci_bus 0000:00: fixups for bus
PCI: bus0: Fast back to back transfers disabled
pci 0000:00:00.0: scanning [bus 01-01] behind bridge, pass 0
pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:01: scanning bus
pci_bus 0000:01: fixups for bus
PCI: bus1: Fast back to back transfers enabled
pci_bus 0000:01: bus scan returning with max=01
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
pci_bus 0000:00: bus scan returning with max=01
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
pci 0000:00:00.0: fixup irq: got 155
pci 0000:00:00.0: assigning IRQ 155
pci 0000:00:00.0: BAR 0: assigned [mem 0x01000000-0x010fffff]
pci 0000:00:00.0: BAR 0: set to [mem 0x01000000-0x010fffff] (PCI address [0x1000000-0x10fffff])
pci 0000:00:00.0: BAR 6: assigned [mem 0x01100000-0x0110ffff pref]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci_bus 0000:00: resource 4 [io 0x1000-0x10000]
pci_bus 0000:00: resource 5 [mem 0x01000000-0x01efffff]
PCI: CLS 64 bytes, default 64
ehci-pci: EHCI PCI platform driver
root@imx6qsabreauto:~# lspci
00:00.0 PCI bridge: Device 16c3:abcd (rev 01)
The logs with kernel 3.0.35-2666-gbdde708:
root@freescale ~$ uname -a
Linux freescale 3.0.35-2666-gbdde708 #6 SMP PREEMPT Wed May 14 11:31:13 JST 2014 armv7l GNU/Linux
root@freescale ~$ dmesg | grep -E 'pci|PCI'
PCI: CLS 0 bytes, default 32
iMX6 PCIe PCIe RC mode imx_pcie_pltfm_probe entering.
PCIE: imx_pcie_pltfm_probe start link up.
IMX PCIe port: link up.
pci 0000:00:00.0: [16c3:abcd] type 1 class 0x000604
pci 0000:00:00.0: reg 10: [mem 0x00000000-0x000fffff 64bit pref]
pci 0000:00:00.0: reg 38: [mem 0x00000000-0x0000ffff pref]
pci 0000:00:00.0: supports D1
pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
pci 0000:00:00.0: PME# disabled
PCI: bus0: Fast back to back transfers disabled
pci 0000:01:00.0: [168c:003e] type 0 class 0x000280
pci 0000:01:00.0: reg 10: [mem 0x00000000-0x001fffff 64bit]
pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
pci 0000:01:00.0: PME# disabled
PCI: bus1: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 14: assigned [mem 0x01000000-0x011fffff]
pci 0000:00:00.0: BAR 0: assigned [mem 0x01200000-0x012fffff 64bit pref]
pci 0000:00:00.0: BAR 0: set to [mem 0x01200000-0x012fffff 64bit pref] (PCI address [0x1200000-0x12fffff])
pci 0000:00:00.0: BAR 6: assigned [mem 0x01300000-0x0130ffff pref]
pci 0000:01:00.0: BAR 0: assigned [mem 0x01000000-0x011fffff 64bit]
pci 0000:01:00.0: BAR 0: set to [mem 0x01000000-0x011fffff 64bit] (PCI address [0x1000000-0x11fffff])
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0: bridge window [io disabled]
pci 0000:00:00.0: bridge window [mem 0x01000000-0x011fffff]
pci 0000:00:00.0: bridge window [mem pref disabled]
root@freescale ~$ lspci
00:00.0 Class 0604: 16c3:abcd
01:00.0 Class 0280: 168c:003e
Thanks.
Hi xiaoxiang
in general you can set GPR8 settings (they define output PCIe signals strength
and sensitivity levels) the same as in kernel 3.0.35,
description can be found in AN4784 p.4
also you can try more new kernels as suggested below
PCIe switch detection problem in I.MX6Q
Best regards
igor
Hi igor
I try to change the GPR8 settings, but it seems to be the same as in kernel 3.0.35.
In file drivers/pci/host/pci-imx6.c in kernel 3.10.17, line 301 in function imx6_pcie_init_phy:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
In file arch/arm/mach-mx6/pcie.c in kernel 3.0.35, line 1013 in function imx_pcie_pltfm_probe:
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN1, 0 << 0, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_FULL, 127 << 18, IOMUXC_GPR8);
imx_pcie_clrset(IOMUXC_GPR8_TX_SWING_LOW, 127 << 25, IOMUXC_GPR8);
I'm confused about this.
I will try some new kernels later.
Best regards
xiaoxiang
Hi igor
Thank you for your quick reply.
I will try it as soon as possible.
Best regards
xiaoxiang