So I finally was able to blow the OTP fuses to have it boot from an MBR based SD card which was good, but then every time I try to boot using either u-boot images or even bootlets from freescale, Bootlets compiled using this. I get in my serial console "HTLLC" repeating which from what I understand is the ROM doing the following.
- H - Header found
- T - Tag found
- L - Load
- L - Load
- C - Call
This is what my efforts have looked like:
▒▒▒▒▒▒▒▒ϱ▒[▒@
▒ ▒▒▒▒▒J▒@%
Data Abort
r14_HTLLCHTLLCLCHTLLCHTLLCLC
Undefined Instruction
r14_unHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCLC
Undefined Instruction
r14_unHTLLCHTLLCHTLLCHTLLCHTLLC
Un▒HTLLCHTLLCLC
Undefined Instruction
r14_unHTLLCHTLLCHTLLCHTLLCLC
Undefined Instruction
r14_unHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLCHTLLC
So after googling and reading here, that seems to indicate that there is likely something wrong with memory or power draw issues. To make sure it's not power draw issues, I am not using the MX233's PMU and instead an external regulated power supply to supply the various required voltages (2.5, 3.3, etc). I will not use an external power supply for the power rails as suggested by Igor.
I am using a AS4C32M16D1-5TCN DRAM ic including length tuned traces with a length of ~750 mil, so I am doubtful it's due to signal integrity issues. Based on discussion here, it seems that there has been varying success.
My questions are these (I am using freescale bootlets since they seem recommended here when trying to work out issues):
- What is the first function the ROM calls? Is it _start() in init-max23.c? Basically, what's the C in HTLLC calling?
- Are these first L's loading into external memory, or the internal SRAM?
- How can I change the speed of the default DRAM assumed in the bootlet?
- I see functions like init_mddr_mt46h32m16lf_96Mhz() but if I stick a printf's at the start of each similar function at the beginning I don't see anything different on my terminal. So I assume these aren't used to setup DRAM.
- Am I SOL for going with the Alliance DRAM? I am not seeing any DRAM's used in the omnilex nor the freescale reference design available on digikey or mouser, so it seems this is true sadly.
Note, this is an extension somewhat of my previous post here.
Edit:
Seems my 2.5v rail is not powering up, even when nothing is connected to it, huh.
Hi hak8or
you are right, there is "some magic" in i.MX23/MX28 boot process.
in general boot process is described in sect.12.11 SD/MMC Boot Mode
MCIMX28RM (the same is for i.MX233), IMX23RM Chapter 35 Boot Modes,
sect.1.1 Boot Stream attached i.MX23_Linux_BSP_UserGuide.pdf,
AN4199 rev.1 9_2010.pdf. Some regulators (such as vddmem) are
not enabled by default, they should be enabled by software, one can find default
values in Chapter 32 Power Supply i.MX23 RM.
Some initialization code is performed by iROM (check attached uboot.db, link.lds,
init-mx23.c from Freescale BSP bootlets sources ) from internal iRAM, then after DDR
initialization uboot/linux code is loaded to DDR.
Ii your case (seems) processor continuosly resets due to some brownout,
before entering to DDR initialization. You can attach jtag debugger and test memory with
debugger and try to run bootlets with jtag. If your board design is based on
olinuxino board, then one needs to use images for olinuxino board.
If board is based on Freescale iMX23 Reference Schematics 
then
one can use Freescale BSP L2.6.31_10.05.00_SDK_SOURCE : Linux 2.6.31 Source Code Files.
Best regards
igor
