MMDC setting in flash_header.S for SABER-SDP

[yuuki]

I have some questions about a MMDC setup in flash_header.S for SABER-SDP.

<Question 1>
For the MMDCx_MDASP setting
In flash_header.S, these are set up as follows.
- 32bit : 4Gb for CS0(2Gb DDR3 x2) => MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x040, 0x00000017)
- 64bit : 8Gb for CS0(2Gb DDR x4) => MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)

However, according to MMDCx_MDASP field descriptions of a reference manual, the following is explained.

000_0000 256Mb
000_0001 512Mb
001_1111 8Gb (1GB)
011_1111 16Gb (2GB) - default
111_1111 32Gb (4GB)

I think that if CS0 is used 4Gb(2Gb DDR3 x2) with 32bit, MMDCx_MDASP setting is 0x0000000F.
Why is MMDCx_MDASP set as 0x00000017?

<Question 2>
For the MMDCx_MAPSR setting
In flash_header.S, these are set up as follows.
- 32bit : MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
- 64bit : MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x404, 0x00011006)

However, according to MMDCx_MAPSR field descriptions of a reference manual, bit19-16 and bit3-1 fields are "Reserved".

Would you teach the reason written in the Reserved domain?
Are these fields for Freescale factories?
Does the user need to write a value in these Fields?

Best Regards,

[alejandrolozan1 · Accepted solution]

Hi,

I believe I can help in the question1.

You have to keep in mind that the DDR address starts at 0x1000_0000. So if you want a rage of 512MB you have to consider that offset.

The MDASP register represents the last address of CS0. That means that the last address must be 0x1000_0000+ 512MB = 0x2FFF_FFFF.

Which corresponds to 0x17 in the MDASP register.

I will delve into the second question.

I hope that helps,

Alejandro

[alejandrolozan1]

Hi,

I have not found any information in regards the second question.

One thing we can try is to modify those values to the reset state, that should not affect the original behavior.

Best Regards,

Alejandro